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MD8412B fujifilm microdevices co., ltd ver 1.10 link(ieee 1394) user's manual
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MD8412B ver 1.10 fujifuilm microdevices co., ltd. i history revision date modified 1.10 6/17/99 first revision of english manual.
MD8412B ii fujifuilm microdevices co., ltd. ver 1.10 keys: msb, lsb of data : msb on the right and lbs on the left negative logic signal description : attached with # at the last end of signal name numeraldescription : binary ****b or **** decimal **** hexadecimal ****h or 0x**** terminology : byte data in 8-bit width word data in 16-bit width quadlet data in 32-bit width octlet data in 64-bit width associated material ieee p1394-1995 standard for a high performance serial bus p1394a draft standard for a high performance serial bus ieee std 1212-1991 command and status register architecture
MD8412B ver 1.10 fujifuilm microdevices co., ltd. iii contents 1 general descriptions .......................................................................................................... .................................................................... 1 1-1 features .................................................................................................................... ............................................................... 1 1-2 applications ................................................................................................................ ............................................................ 1 1-3 internal block diagram ...................................................................................................... ...................................................... 2 1-4 functional outlines ......................................................................................................... ......................................................... 3 1-4-1 host interface............................................................................................................ .............................................. 3 1-4-2 phy interface ............................................................................................................. ............................................ 3 1-4-3 transmitter............................................................................................................... ............................................... 3 1-4-4 receiver .................................................................................................................. ................................................ 3 1-4-5 built-in buffer ........................................................................................................... .............................................. 3 1-4-6 isochronous transfer functions............................................................................................ .................................... 4 2 terminal description.......................................................................................................... .................................................................... 5 2-1 functional description for terminals ........................................................................................ ............................................... 5 3 control register .............................................................................................................. ....................................................................... 7 3-1 method of register access................................................................................................... ..................................................... 7 3-2 contents of register ........................................................................................................ ......................................................... 8 3-2-1 version register .......................................................................................................... ........................................... 8 3-2-2 control register.......................................................................................................... ............................................ 8 3-2-3 node identification register.............................................................................................. ................................... 11 3-2-4 reset register ............................................................................................................ ........................................... 12 3-2-5 asyncronous buffer size set register ...................................................................................... ........................... 13 3-2-6 isochronous buffer size set register ...................................................................................... ............................. 14 3-2-7 packet control register ................................................................................................... ..................................... 15 3-2-8 diagnostic status register................................................................................................ .................................... 17 3-2-9 phy control register...................................................................................................... ....................................... 19 3-2-10 atretries register ....................................................................................................... ........................................ 20 3-2-11 cycle timer register..................................................................................................... ....................................... 21 3-2-12 isochronous packet length register ...................................................................................... ............................. 22 3-2-13 isochronous configuration register 1,2,3,4 ............................................................................... .......................... 22 3-2-14 atf data register........................................................................................................ ........................................ 25 3-2-15 arf data register........................................................................................................ ........................................ 25 3-2-16 itf/irf data register .................................................................................................... ...................................... 26 3-2-17 irf data register ........................................................................................................ ......................................... 26 3-2-18 buffer status and control register....................................................................................... ................................ 27
MD8412B iv fujifuilm microdevices co., ltd. ver 1.10 3-2-19 interrupt register ....................................................................................................... ........................................... 28 3-2-20 interrupt mask register.................................................................................................. ....................................... 31 3-2-21 tgo register ............................................................................................................. ............................................ 31 3-2-22 bus time register........................................................................................................ ......................................... 32 3-2-23 atretries register ....................................................................................................... .......................................... 33 3-3 registers ................................................................................................................... ............................................................. 34 4 data format ................................................................................................................... ....................................................................... 36 4-1 asynchronous ................................................................................................................ ........................................................ 36 4-1-1 quadlet transmit.......................................................................................................... ......................................... 36 4-1-2 block transmit............................................................................................................ .......................................... 37 4-1-3 quadlet receive ........................................................................................................... ......................................... 38 4-1-4 block receive ............................................................................................................. .......................................... 40 4-2 asynchronous stream......................................................................................................... ................................................... 42 4-2-1 transmit .................................................................................................................. .............................................. 42 4-2-2 receive................................................................................................................... ............................................... 43 4-3 isochronous................................................................................................................. ........................................................... 44 4-3-1 normal mode ............................................................................................................... ......................................... 44 4-3-1-1 transmit................................................................................................................ .......................... 44 4-3-1-2 receive ................................................................................................................. .......................... 45 4-3-2 auto-mode ................................................................................................................. ........................................... 46 4-3-2-1 transmit................................................................................................................ .......................... 46 4-3-2-2 receive ................................................................................................................. .......................... 46 4-4 snoop....................................................................................................................... .............................................................. 47 4-5 selfid packet............................................................................................................... .......................................................... 48 4-6 phy control packet .......................................................................................................... .................................................... 50 4-6-1 phy control packet transmit ............................................................................................... ............................... 50 4-6-2 phy control packet receive ................................................................................................ ................................ 50 4-7 code........................................................................................................................ ............................................................... 50 5 functional description ........................................................................................................ ................................................................. 54 5-1 host interface.............................................................................................................. ........................................................... 54 5-1-1 register access timing.................................................................................................... ....................................... 54 5-1-2 host bus width............................................................................................................ ........................................... 55 5-1-3 dma transfer .............................................................................................................. .......................................... 56 5-1-4 interrupt processing...................................................................................................... ......................................... 57 5-2 phy-chip interface.......................................................................................................... ...................................................... 58 5-2-1 connecting method ......................................................................................................... ...................................... 58 5-2-2 phy-chip control .......................................................................................................... ........................................ 59 5-2-3 request................................................................................................................... ............................................... 60
MD8412B ver 1.10 fujifuilm microdevices co., ltd. v 5-2-3-1 lreq .................................................................................................................... ......................... 60 5-2-4 transfer.................................................................................................................. ............................................... 62 5-2-4-1 status request .......................................................................................................... ...................... 62 5-2-4-2 singlepackettransmit .................................................................................................... ................ 63 5-2-4-3 concatenated packet transmit ........................................................................................... 64 5-2-4-4 receive................................................................................................................. .......................... 65 5-2-5 phy-link i/f reset timing ................................................................................................. .............................. 66 5-3 buffer access ............................................................................................................... .......................................................... 68 5-3-1 buffer configuration ...................................................................................................... ....................................... 68 5-3-2 size setting for each sub-buffer .......................................................................................... .................................. 69 5-3-3 buffer access by bus width ................................................................................................ ................................... 70 5-3-3-1 soft access............................................................................................................. ......................... 70 5-3-3-2 dma access .............................................................................................................. ..................... 71 5-3-4 buffer control............................................................................................................ ............................................ 73 5-3-4-1 asynchronous buffer control ............................................................................................. ............ 73 5-3-4-1-1 transmission buffer.................................................................................................. 74 5-3-4-1-2 reception buffer ...................................................................................................... . 75 5-3-4-2 isochronous buffer control .............................................................................................. ............... 76 5-3-4-2-1 normal mode ........................................................................................................... . 76 5-3-4-2-2 auto-mode............................................................................................................. ... 76 5-4 isochronous transfer control (auto-mode).................................................................................... ......................................... 77 5-4-1 length control............................................................................................................ ........................................... 77 5-4-2 transmission start / stop control......................................................................................... .................................. 77 5-4-3 sync control .............................................................................................................. ............................................ 77 5-5 cycle master ................................................................................................................ ......................................................... 78 5-6 32-bit crc .................................................................................................................. .......................................................... 78 5-7 control flow ................................................................................................................ .......................................................... 78 5-7-1 asynchronous transmission................................................................................................. ................................ 79 5-7-2 asynchronous reception .................................................................................................... .................................. 81 5-7-3 isochronous transmission .................................................................................................. .................................. 84 5-7-4 isochronous reception ........................................................................................................................... 85 5-7-5 isochronous transmission (auto-mode) ...................................................................................... ......................... 86 5-7-6 isochronous reception (auto-mode) ...................................................................................................... 87 5-8 asynchronous stream transfer flow ........................................................................................... ........................................... 89 5-8-1 asynchronous stream transmission .......................................................................................... ............................ 89 5-8-2 asynchronous stream reception............................................................................................. ............................... 89 5-9 command-reset packet processing ............................................................................................. ......................................... 90 5-10 bus number for asynchronous packet transmission ............................................................................ ................................. 90
MD8412B vi fujifuilm microdevices co., ltd. ver 1.10 6 electrical characteristics .................................................................................................... .................................................................. 91 6-1 absolute rating ............................................................................................................. ........................................................ 91 6-2 recommended operating condition ............................................................................................. ........................................ 91 6-3 dc characteristics.......................................................................................................... ....................................................... 92 6-4 ac characteristics.......................................................................................................... ....................................................... 93 7 pin assignment and package outline............................................................................................ ....................................................... 98 7-1 pin assignment.............................................................................................................. ........................................................ 98 7-2 package outline............................................................................................................. ........................................................ 99 appendix 1 i/o status......................................................................................................... ..................................................................... 100 appendix 2 example circuit for ac connection.................................................................................. .................................................... 101 notes .......................................................................................................................... ............................................................................... 102
MD8412B ver 1.10 fujifuilm microdevices co., ltd. vii figure and table contents figure 1-3-1 MD8412B block diagram.............................................................................................. ......................................... 2 figure 3-1-1 register address on 8-bit bus ...................................................................................... .......................................... 7 figure 3-1-2 register address on 16-bit bus ..................................................................................... ......................................... 7 figure 5-1-1 host access timing................................................................................................. .............................................. 54 figure 5-1-2 dma transfer timing................................................................................................ ........................................... 56 figure 5-1-3 dreq negate timing (wr#) ........................................................................................... .................................... 57 figure 5-1-4 dreq negate timing (rd#) ........................................................................................... ..................................... 57 figure 5-2-1 connection between MD8412B and phy-chip............................................................................ ........................ 58 figure 5-2-2 connection between MD8412B and md8404 .............................................................................. ........................ 59 figure 5-2-3 lreq stream........................................................................................................ ................................................. 60 figure 5-2-4 status request..................................................................................................... ................................................... 62 figure 5-2-5 singlepackettransmit ............................................................................................... ............................................. 63 figure 5-2-6 concatenated packet transmit ....................................................................................... ....................................... 64 figure 5-2-7 receive ............................................................................................................ ...................................................... 65 figure 5-2-8 speed code (sp[0:7]) ............................................................................................... ............................................. 65 figure 5-2-9 lps output waveform in ac connection............................................................................... ................................ 66 figure 5-2-10 phyifrst="0"; phy-link i/f reset sequence in ac connection........................................................ ........... 67 figure 5-2-11 phyifrst="1"; phy-link i/f reset sequence in ac connection........................................................ ........... 67 figure 5-3-1 buffer assignment in cases other than isomode="011b"............................................................... ..................... 68 figure 5-3-2 buffer assignment in the case of isomode="011b" .................................................................... ......................... 69 figure 5-3-3 sub-buffer size assignment ......................................................................................... ........................................ 70 figure 5-3-4 register operation (atf) for 8-bit width soft access ............................................................... ......................... 70 figure 5-3-5 register operation (arf) for 8-bit width soft access............................................................... ......................... 71 figure 5-3-6 register operation (atf) for 16-bit width soft access .............................................................. ........................ 71 figure 5-3-7 register operation (arf) for 16-bit width soft access.............................................................. ........................ 71 figure 5-3-8 register operation (atf) for 8-bit width dma access ................................................................ ..................... 72 figure 5-3-9 register operation (arf) for 8-bit width dma access ................................................................ ..................... 72 figure 5-3-10 register operation (atf) for 16-bit width dma access .............................................................. ..................... 73 figure 5-3-11 register operation (arf) for 16-bit width dma access .............................................................. ..................... 73 figure 5-3-12 concept of atf operation .......................................................................................... .......................................... 74 figure 5-3-13 concept of arf operation.......................................................................................... .......................................... 75 figure 5-7-1 atf transmission flow -1........................................................................................... ......................................... 79 figure 5-7-2 atf transmission flow -2........................................................................................... ......................................... 80 figure 5-7-3 arf reception flow -1.............................................................................................. ........................................... 81 figure 5-7-4 arf reception flow -2.............................................................................................. ........................................... 82 figure 5-7-5 itf transmission flow.............................................................................................. ............................................ 84
MD8412B viii fujifuilm microdevices co., ltd. ver 1.10 figure 5-7-6 irf reception flow ................................................................................................. ..............................................85 figure 5-7-7 itf transmission flow (auto-mode & syncen="1") ..................................................................... .......................86 figure 5-7-8 irf reception flow (auto-mode & syncen="1") ........................................................................ .........................87 figure 6-4-1 host interface ac characteristics (read/write)..................................................................... ...............................94 figure 6-4-2 host interface ac characteristics (reset) .......................................................................... ...................................95 figure 6-4-3 interface ac characteristics (dma) ................................................................................. ....................................95 figure 6-4-4 host interface ac characteristics (cyclein/out) .................................................................... .......................95 figure 6-4-5 phy ac characteristics (sclk)...................................................................................... .....................................96 figure 6-4-6 phy ac characteristics (ctl, d) .................................................................................... ....................................97 figure 6-4-7 phy ac characteristics (lreq) ...................................................................................... ....................................97 figure 6-4-8 phy ac characteristics (lps)....................................................................................... .......................................97 table 2-1-1 MD8412B terminal table (1) .......................................................................................... .......................................5 table 2-1-2 MD8412B terminal table (2) .......................................................................................... .......................................6 table 3-3-1 registers 1......................................................................................................... .....................................................34 table 3-3-2 registers 2......................................................................................................... .....................................................35 table 4-1-1 quadlet transmit format (asynchronous) .............................................................................. ...............................36 table 4-1-2 block transmit format (asynchronous) ................................................................................ ................................37 table 4-1-3 quadlet receive format (asynchronous)............................................................................... ................................38 table 4-1-4 block receive format (asynchronous)................................................................................. .................................40 table 4-2-1 asynchronous stream transmit format ................................................................................. ................................42 table 4-2-2 asynchronous stream receive format.................................................................................. .................................43 table 4-3-1 block transmit format (isochronous: normal) ......................................................................... .............................44 table 4-3-2 block receive format (isochronous: normal) .......................................................................... ..............................45 table 4-3-3 block transmit format (isochronous: auto)........................................................................... ................................46 table 4-3-4 block receive format (isochronous: auto) ............................................................................ ................................46 table 4-4-1 snoop receive format ................................................................................................ ............................................47 table 4-5-1 selfid packet receive format (first quadlet) ........................................................................ .................................48 table 4-5-2 selfid packet receive format (selfid packet #0)..................................................................... ............................48 table 4-5-3 selfid packet receive format (selfid packet #1, #2, & #3)........................................................... ......................48 table 4-5-4 selfid packet receive format (last quadlet)......................................................................... .................................48 table 4-5-5 selfid packet receive format (pn) ................................................................................... .....................................48 table 4-6-1 phy control packet format (first quadlet) ........................................................................... ..................................50 table 4-7-1 list of retry code.................................................................................................. .................................................50 table 4-7-2 list of transaction code (tcode).................................................................................... ........................................51 table 4-7-3 list of bus number / node number .................................................................................... ..................................51 table 4-7-4 list of data length (data length)................................................................................... ......................................51 table 4-7-5 list of extension transaction code (extend tcode) ................................................................... ..........................52 table 4-7-6 list of speed codes (spd) ........................................................................................... ...........................................52
MD8412B ver 1.10 fujifuilm microdevices co., ltd. ix table 4-7-7 list of acknowledge codes (ack) ..................................................................................... ................................... 53 table 5-1-2 little / big endian mode ............................................................................................ ........................................... 55 table 5-1-1 valid host data bus accessed from the host.......................................................................... ............................. 55 table 5-1-3 dreq signal assert / negate conditions .............................................................................. ............................... 56 table 5-2-1 phy-chip control mode 1............................................................................................. ....................................... 59 table 5-2-2 phy-chip control mode 2............................................................................................. ....................................... 59 table 5-2-3 request format ...................................................................................................... ................................................ 60 table 5-2-4 speed format ........................................................................................................ ................................................. 60 table 5-2-5 read register format ................................................................................................ ............................................ 61 table 5-2-6 write register format ............................................................................................... ............................................ 61 table 5-2-7 acceleration control format ......................................................................................... ........................................ 61 table 5-2-8 request type ........................................................................................................ ................................................. 61 table 5-2-9 status request format ............................................................................................... ............................................ 62 table 5-2-10 lps output ......................................................................................................... .................................................... 66 table 5-2-11 lps output characteristics in ac connection ........................................................................ ............................. 66 table 5-7-1 status of interrupt and fifo during arf reception ................................................................... ......................... 83 table 5-7-2 status of interrupt and fifo during irf, tf/irf reception........................................................... ..................... 88 table 5-8-1 asynchronous stream transmit format................................................................................. ................................ 89 table 5-8-2 asynchronous stream receive format .................................................................................. ................................ 89 table 6-4-1 host interface ac characteristics ................................................................................... ...................................... 93 table 6-4-2 phy ac characteristics .............................................................................................. .......................................... 96
MD8412B x fujifuilm microdevices co., ltd. ver 1.10 memo
MD8412B ver 1.10 fujifuilm microdevices co., ltd. 1 1 general descriptions the MD8412B is a link layer controller for high-speed serial buses, designed in accordance with the ieee draft standard, ieee 1394 -1995. it involves all necessary functions for the link layer, and also functions to relieve the burden of the system for isochro- nous transfer. therefore, it is suitable for being incorporated in equipment on the side of peripheral terminals. 1-1 features - packing for transmission and unpacking for reception, according to ieee 1394-1995 and p1394a. - cycle master support - parity generation and error detection by 32-bit crc - detection of dropped cycle start messages - direct with phy chip (md8402) and interface by ac coupling - 3-speed support of 100/200/400mb/sec. - control of the no. of transfers in each cycle during isochronous transfer - automatic insertion of a header in isochronous packet during transmission and automatic header separation and routing during reception - support of outbound retry sequence - feasibility of selecting a host-bus width from 8/16/32-bit, enabling easy connection with a general-purpose mpu/micro- computer - support of both big and little-endians during selection of host bus 16/32-bit 1-2 applications - digital camera - digital vtr - digital audio - electronic musical instruments - scanner - printer - various storages
MD8412B 2 fujifuilm microdevices co., ltd. ver 1.10 1-3 internal block diagram figure 1-3-1 MD8412B block diagram interrupt control unit transmitter int# ha(6:0) hd(31:0) cs# wr# rd# dreq dack# host i/f reset# ube# uwe# itstart internal registers buffer manager buffer memory (2kb) cycle timer header controller crc cycle monitor receiver phy i/f link core d(7:0) ctl(1:0) lreq sysclk
MD8412B ver 1.10 fujifuilm microdevices co., ltd. 3 1-4 functional outlines 1-4-1 host interface the host interface is composed of asynchronous buses in a width of sram-style 8/16/32-bit. since dma control func- tions are provided inside, dreq signals can be generated according to the state of a buffer, enabling high-speed data trans- fer. bus width changeover of 8/16/32 can be controlled by a signal of uwe#, ube#, a1, or a0. it is possible to change reg- ister and buffer access operation. all registers can be directly accessed from the host. in dma transfer, internal buffer selection is effected to enable gaining access to the selected buffer. 1-4-2 phy interface an interface is available, which enables direct connection with the phy chip to process a physical layer according to ieee 1394. either 100mbps or 200mbps is acceptable for the phy chip to be connected. in the ieee1394 draft, the connection mode for the phy and link chips is classified to the following two kinds: - dc connection - ac connection this ic supports both kinds of connections. 1-4-3 transmitter the transmitter reads out data from an asynchronous transmission buffer or an isochronous transmission buffer in the MD8412B, and sends out a phy interface packet through formatting into each packet format defined by ieee p1394. if the cycle master bit is "1" and the node using the MD8412B is a route, then a cycle start packet is also sent out to indicate the head of the isochronous cycle. 1-4-4 receiver the receiver receives a packet from the phy interface and identifies if this packet is the one to be acquired by the node of MD8412B. if it is found as an asynchronous packet, it is identified with a node address of MD8412B. if it is an isochro- nous packet, it is identified with a preset channel number. if a packet is headed to this node, routing is effected toward the asynchronous reception buffer or the isochronous reception buffer by writing the data therein. for a broadcast packet and the snoop mode, no judgment is effected and data are written in their buffer. 1-4-5 built-in buffer the MD8412B incorporates a buffer in 512 32(bit) configuration with a capacity of 2k-byte in total. this is a temporary buffer intended for data rate absorption between transmitter and host bus. the host performs data access to this buffer. the MD8412B controls this buffer by dividing it into a maximum of 4 areas. two of the divided areas are used at random for asynchronous transmission and reception. the remaining two areas depend on isochronous modal setting. each buffer size is designated at the register. status information, such as full or empty in the buffer, can be known at the host in the divided unit.
MD8412B 4 fujifuilm microdevices co., ltd. ver 1.10 1-4-6 isochronous transfer functions the MD8412B possesses isochronous functions. it incorporates a cycle timer so that a cycle start packet can be transmit- ted in the unit of 125?ec when the node seizing the MD8412B is of the cycle master. its trigger is an 8khz signal entered through the cyclein pin, obtained as a result of generation of a clock signal of 49.152mhz, coming from the phy chip. when the above-mentioned node is not of the cycle master, synchronism with the cycle master is secured through com- pensation of the cycle master within the MD8412B, based on the value of that packet, each time a cycle start packet is received from another cycle master node. the MD8412B is provided with two types of isochronous modes. one is a mode intended to gain access to the host with a packet image. the other is a mode for host access with an image of data themselves. (to be described in detail later) the user determines the mode, according to the nature of data source to be handled in the isochronous transfer mode.
MD8412B ver 1.10 fujifuilm microdevices co., ltd. 5 2 terminal description 2-1 functional description for terminals signal type pin no. of pin contents phy interface sclk i 72 1 master clock: a 49.152mhz clock signal fed from the phy chip. the MD8412B employs this clock as a master clock signal. usually connected to this signal pin of the phy chip. lreq o 74 1 link request: the MD8412B uses this signal when making a request of register access in the phy chip and when using a serial bus. usually connected to this signal pin of the phy chip. ctl(1:0) i/o 69, 70 2 phy-link control: an interface control signal for data transmission/ reception with the phy chip. usually connected to this signal pin of the phy chip. d(7:0) i/o 57, 58, 60, 61, 63, 64, 66, 67 8 phy-link data bus: a data bus for data transmission/reception with the phy chip. d(1:0) is used for packet transmission/reception at 100mbps, d(3:0) is used at 200mbps, and all bits are used at 400mbps. lps o 75 link status: a lps signal to phy. output in the following combination available by register setting. direct input lpson bit lps output hl l hh h ll l lh approx. 0.6 to 3.6mhz clock (duty 33%) host interface ha(6:0) i 92, 93, 95, 96, 97, 99, 100 7 host address: a host address for register selection hd(31:0) i/o 1, 2, 4~6, 8~10, 12~14, 16~18, 20~22, 24~26, 28~30, 32~34, 36~38, 40~42 32 host data bus: a data bus for register data access. in combination with other signals, effective bit width is changeable among 31, 16, and 8 bits. combinations will described later. wr# i 89 1 write enable: a writing signal for host data bus. rd# i 88 1 read enable: a reading signal for host data bus. cs# i 91 1 chip select: chip selection signal for host data bus table 2-1-1 MD8412B terminal table (1)
MD8412B 6 fujifuilm microdevices co., ltd. ver 1.10 signal type pin no. of pin contents uwe# i 87 1 upper write enable: an enable signal of the upper word (16-bit) for a 32- bit data bus. with active low of this signal, the upper 16-bit is also asserted on the data bus. ube# i 85 1 upper byte enable: an enable signal of the upper byte in 16-bit of the upper/lower word for a 32-bit data bus. with active low of this signal, the upper 8-bit is also asserted in the upper and lower words, respectively. dreq o 83 1 data request: a request signal for dma transfer. asserted only for packet and data transfer. dack# i 84 1 data acknowledge: an acknowledge signal for dma transfer. asserted only for packet and data transfer. int# o 81 1 interrupt signal: an interrupt signal for announcement to the host. this signal is asserted when any factor arises in the interrupt register. reset# i 80 1 reset: a system reset signal of the MD8412B. others cyclein i 77 1 isochronous cycle input: an external clock for counting the internal cycle timer in 8khz unit. when cyclesource bit is "1" in the control register, this clock becomes valid. cycleout o 78 1 isochronous cycle output: a cycle clock output generated by counting the internal cycle timer of the MD8412B. itstart i 44 1 isochronous transmission start signal in itstart auto-mode. direct i 55 1 phy i / f direct select signal: a changeover signal used to select direct or isolation connection of i / f with phy. 0: isolation connection 1: direct connection test terminals inp(2:0) i 45, 51, 52 1 a signal for testing. in general, inp (2:0) is to be connected to the vss. testen i 46 1 a signal for testing. in general, testen is to be connected to the vss. tlink i 47 1 a signal for testing. in general, tlink is to be connected to the vss. tlinksep i 49 1 a signal for testing. in general, tlinksep is to be connected to the vss. trful i 50 1 a signal for testing. in general, trful is to be connected to the vss. test(1:0) i 53, 54 1 a signal for testing. in general, test(1:0) is to be connected to the vss. power supply vdd i 7, 19, 31, 39, 56, 62, 68, 79, 86, 94 7 3.3v power supply. vss i 3, 11, 15, 23, 27, 35, 43, 48, 59, 65, 71, 73, 76, 82, 90, 98 32 gnd table 2-1-2 MD8412B terminal table (2)
MD8412B ver 1.10 fujifuilm microdevices co., ltd. 7 3 control register 3-1 method of register access for 32-bit access, each register gains a description of header address only. accordingly, the following addresses are used for 8- and 16-bit. the read-only register should be used for the read-out operation only. the writing operation should not be performed at that time. if this operation is actually attempted, the result from such an operation is not assured. 76543210 index +3 byte(adrs+3) 15 14 13 12 11 10 9 8 index +2 byte(adrs+2) 23 22 21 20 19 18 17 16 index +1 byte(adrs+1) 31 30 29 28 27 26 25 24 index byte(adrs) figure 3-1-1 register address on 8-bit bus 76543210 index +2 word-l(adrs+2) 15 14 13 12 11 10 9 8 word-h(adrs+2) 23 22 21 20 19 18 17 16 index word-l(adrs) 31 30 29 28 27 26 25 24 word-h(adrs) figure 3-1-2 register address on 16-bit bus
MD8412B 8 fujifuilm microdevices co., ltd. ver 1.10 3-2 contents of register 3-2-1 version register index 00h initial value 0001 0002h this register provides chip version and revision number. it is effective in software for ieee 1394-link chip control in the future. bit 15~0 revision : revision number of ic chip (r-initial value: 0002h) indicates the revision number of MD8412B. this figure begins with "0" and increases each time revision is made. bit 31~16 version : version number of ic chip (r-initial value: 0001h) indicates the version number of MD8412B. "0001h" is always read out of the MD8412B. 3-2-2 control register index 04h initial value 0003 0001h this register makes settings for each operational configuration of the chip, enable, etc. generally, this register setting is made shortly after the closure of the power switch. the MD8412B configuration should have been defined in advance. 76543210 revision 15 14 13 12 11 10 9 8 revision 23 22 21 20 19 18 17 16 version 31 30 29 28 27 26 25 24 version 76543210 phyifrst lpson receiveen transmiten 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 isomode cyclesource cyclemaster cycletimeren 31 30 29 28 27 26 25 24 dmawidth little
MD8412B ver 1.10 fujifuilm microdevices co., ltd. 9 bit 0 transmiten : transmit enable bit (rw- initial value: 1b) 0 = transmitter disabled 1 = transmitter enabled setting is made to decide if the MD8412B transmitter is enabled or not. in the case of enable, the following transmission is performed: - asynchronous packet - cycle start packet with a cycle master bit enabled - isochronous packet for cycle start this bit is automatically set at " 1 " when a request for bus reset is received from the phy chip. bit 1 receiveen : receive enable bit (rw- initial value: 0b) 0 = receiver disabled 1 = receiver enabled setting is made to decide if the MD8412B receiver is enabled or not. in the case of enable, the following reception is performed: - synchronous packet addressed from another node to this node - isochronous packet of the designated channel - reception in snoop mode bit 4 lpson : ink power status on bit (rw- initial value: 0b) this bit is used to control the lps signal supplied to the phy chip. according to the status of the direct terminal, contents of output are different. bit 7 phyifrst : phy-link i/f reset bit (rw- initial value: 0b) selection is made to determine whether the initialization of phy-link i/f is performed at the time of default or at the timing defined by p1394a. 0 = selection is performed at the timing of default. 1 = selection is performed at the timing defined by p1394a. bit 16 cycletimeren : cycle timer enable bit (rw- initial value: 1b) 0 = cycle timer disabled 1 = cycle timer enabled setting is made to decide if the MD8412B cycle timer is enabled or not. bit 17 cyclemaster : cycle master bit (rw- initial value: 1b) 0 = receiving a cycle start packet from a node in another route, cycle timer control is effected. to be set at " 1 " when this node cannot belong to an ordinary route. 1 = when this bit is " 1 " cycle start packet is generated each time the MD8412B cycle timer carries. direct lpson lps output 10 0 11 1 00 0 01 approx. 0.6 to 3.6mhz clock (duty 33%)
MD8412B 10 fujifuilm microdevices co., ltd. ver 1.10 bit 18 cyclesource : cycle source bit (rw- initial value: 0b) 0 = the cycle timer is counted with 24.576mhz of the master clock that is a clock signal fed from the phy chip, in order to control the isochronous cycle. 1 = the cycle timer is updated at the rising point of a signal entered from the cyclein terminal. the updating source is set up for the internal timer that is in charge of isochronous time control. bit 22~20 isomode : isochronous mode bit (rw- initial value: 000b) settings of normal mode and auto-mode are made for both isochronous transmission and reception. the number of corresponding isochronous channels is as specified below, according to the mode of transmission or reception: bit 24 little : little-endian bit (rw- initial value: 0b) 0 = data of atf, arf, itf, irf buffer are handled as a big-endian. 1 = data of atf, arf, itf, irf buffer are handled as a little-endian. bit 29~28 dmawidth : dma transfer data width bit (rw- initial value: 00b) 00 = 8-bit (byte) transfer 01 = 16-bit (word) transfer 10 = 32-bit (quadlet) transfer 11 = reservation isochronous mode transmission reception 000 normal normal 001 normal auto 010 auto normal 011 - auto 100 auto auto 101 - normal 1xx reserved transmission in normal mode no. of channels for packets where buffer areas are not full for each isochronous cycle. for each cycle, however, the number of packets for each channel is limited to 1. transmission in auto-mode limited to 1 channel. a normal mode is used if more channels are needed to support. reception in normal mode for "101", packets for maximum of 4 channels can be received. for "010", however, the number of channels is limited to 3. setting for chan- nel designation is made at the isoconfigreg. reception in auto-mode limited to 1 channel. only for "011", however, 2-channel reception is possible. in this case, routing is effected on the buffer for each channel. (at that time, isochronous transmission is disabled.)
MD8412B ver 1.10 fujifuilm microdevices co., ltd. 11 3-2-3 node identification register index 08h initial value 0000 ffffh bit 5~0 nodenumber : node number bit (rw- initial value: 3fh) this value is used to set up a 6-bit node number to be defined in the ieee1212 space. during transmission, this value is used in the source area of the ieee p1394 packet format header. when receiving a packet, the des- tination node number of this packet is examined and when found to coincide with this value, the packet is received. it is rejected in otherwise case. usually, the node number is read from the phy chip and setting is made at this register after the completion of bus reset and end of self-identification phase. bit 15~6 busnumber : bus number bit (rw- initial value: 3ffh) this value is used to set up a 10-bit bus number to be defined in the ieee1212 space. during transmission, this value is used in the source area of the header area in the ieee p1394 packet format header. during recep- tion, this busnumber bit is disregarded. bit 31 idvalid : id valid bit (rw- initial value: 00b) 0 = only the packet (broadcast packet) is received, where the value of nodenumber is addressed as " 3fh " in other cases, the packet is rejected. 1 = only the packet is received, for which the value of nodenumber is addressed in the ieee1212 address space set by the above-mentioned register. a broadcast packet is also received. when the state of bus reset arises, this register is automatically cleared to " 0 " the node number is generally determined after the completion of bus reset and end of self-identification phase. accordingly, this value is set up after the host has set it in the nodenumber register. 76543210 busnumber-l nodenumber 15 14 13 12 11 10 9 8 busnumber-h 23 22 21 20 19 18 17 16 31 30 29 28 27 26 25 24 idvalid
MD8412B 12 fujifuilm microdevices co., ltd. ver 1.10 3-2-4 reset register index 0ch initial value 0000 0000h bit 0 resetatf : reset atf bit: (rw- initial value: 0b) 0 = normal condition 1 = buffer area initialized for asynchronous transmission only the buffer area for asynchronous transmission is returned to initial state. at that time, however, all data in that area are lost. all status flags of this buffer are also returned to their initial state. when " 1 " is set, and when internal initialization is completed later, this bit is automatically set at "0". bit 1 resetitf/irf : reset itf/irf bit (rw- initial value: 0b) 0 = normal condition 1 = buffer area initialized for isochronous transmission/reception when isomode setting is for other than " 011 " isochronous transmission buffer is restored to initial conditions. when it is for " 011 " mode, only the buffer area is restored to initial conditions for isochronous channel reception designated by isochronous configuration 2,3 register. at that time, however, all data in that area are lost. all sta- tus flags of this buffer are also returned to their initial state. when "1" set, and when internal initialization is completed later, this bit is automatically set at "0". bit 2 resetarf : reset arf bit (rw- initial value: 0b) 0 = normal condition 1 = buffer area initialized for asynchronous reception only the buffer area for asynchronous reception is returned to initial state. at that time, however, all data in that area are lost. all status flags of this buffer are also returned to their initial state. when "1" is set, and when internal initialization is completed later, this bit is automatically set at "0". bit 3 resetirf : reset irf bit (rw- initial value: 0b) 0 = normal condition 1 = buffer area initialized for isochronous reception only the buffer area for isochronous channel reception specified by the isochronous configuration register is returned to initial state. at that time, however, all data in that area are lost. all status flags of this buffer are also returned to their initial state. when "1" set, and when internal initialization is completed later, this bit is automatically set at "0" . 76543210 resetdma resetlink resettx resetirf resetarf resetitf/irf resetatf 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 31 30 29 28 27 26 25 24
MD8412B ver 1.10 fujifuilm microdevices co., ltd. 13 bit 4 resettx : reset transmitter bit (rw- initial value: 0b) 0 = normal condition 1 = transmitter being reset transmitter is reset to set up a transmission-enabled condition. if a packet is being transmitted, that transmis- sion is supported. when "1" set, and when internal initialization is completed later, this bit is automatically set at "0" . bit 5 resetlink : reset link core bit (rw- initial value: 0b) 0 = normal condition 1 = link core being reset link core is reset to support all operation. when "1" set, and when internal initialization is completed later, this bit is automatically set at "0" . bit 6 resetdma : reset dma bit (rw- initial value: 0b) 0 = normal condition 1 = dma control being reset dma control is reset to set up a condition enabling dma transfer. dma is required to complete transfer in the quadlet unit. the dma transfer pointer in the quadlet unit is cleared with this bit and the pointer is set in the header position in the quadlet unit. when "1" is set, and when internal initialization is completed later, this bit is automatically set at "0" . 3-2-5 asyncronous buffer size set register index 10h initial value 007f 00ffh in this register, an assignment size is specified to assign an asynchronous area to the internal buffer having a 2kb capac- ity. this size is specified in the quadlet unit. max configuration size is 511quadlet. bit 8~0 atotalsize : asynchronous total buffer bit (rw- initial value: 0ffh) all buffer sizes for asynchronous transmission and reception are specified in the quadlet unit. all data (iso- chronous also) remaining in the buffer before modification are abandoned. bit 24~16 arxbuffersize : asynchronous receive buffer size bit (rw- initial value: 07fh) buffer size for asynchronous reception is specified in the quadlet unit. in this case, this value must always be smaller than the one set by totalsize. and configuration beyond 5quadlet. if this value is changed, all data remaining in the asynchronous transmission/reception buffer are abandoned. there is no influence in the isoch- ronous domain. 76543210 atotalsize 15 14 13 12 11 10 9 8 atotalsize 23 22 21 20 19 18 17 16 arxbuffersize 31 30 29 28 27 26 25 24 arxbuffersize
MD8412B 14 fujifuilm microdevices co., ltd. ver 1.10 by the above-mentioned two setting values, the transmission buffer size is defined as: atansmitbuffersize = atotalsize - arxbuffersize 3-2-6 isochronous buffer size set register index 14h initial value 007f 00ffh in this register, an assignment size is specified to assign an isochronous area to the internal buffer having a 2kb capacity. this size is specified in the quadlet unit. max configuration size is 511quadlet. bit 8~0 itotalsize : isochronous total buffer bit (rw- initial value: 0ffh) all buffer sizes for isochronous transmission and reception are specified in the quadlet unit. when isomode is "011" however, transmission buffer is lost and setting is made in the receiving buffer for two channels. bit 24~16 irxbuffersize : isochronous receive buffer size bit (rw- initial value: 07fh) buffer size for isochronous reception is specified in the quadlet unit. in this case, this value must always be smaller than the one set by totalsize. if this value is changed, all data remaining in the isochronous transmis- sion/reception buffer are abandoned. if isomode is not " 011 " the transmission buffer size is defined as follows by the above-mentioned two setting values: itansmitbuffersize = itotalsize - irxbuffersize when isomode is " 011b " contents of the isochronous configuration 3 register are stored in the buffer being set by the irxbuffersize, and contents of the isochronous configuration 2 register are stored in the buffer being set by the itransmitbuffersize. when isomode is " 101b " itotalsize and irxbuffersize must be set at the same value. 76543210 itotalsize 15 14 13 12 11 10 9 8 itotalsize 23 22 21 20 19 18 17 16 irxbuffersize 31 30 29 28 27 26 25 24 irxbuffersize
MD8412B ver 1.10 fujifuilm microdevices co., ltd. 15 3-2-7 packet control register index 18h initial value 0000 1020h bit 1 enacc : ack acceleration on bit (rw- initial value: 0b) 0 = transmission of an asynchronous packet by ackacceleration is disabled. 1 = transmission of an asynchronous packet by ackacceleration is enabled. setting is made to determine whether the transmission of an asynchronous packet by ackacceleration is enabled or not. isomode becomes effective only when " 000b " , " 001b " , " 011b " , " 101b " are set up. bit 2 multi : multi speed concatination on bit (rw- initial value: 0b) 0 = multi-speed concatenation transmission of isochronous packet is disabled. 1 = multi-speed concatenation transmission of isochronous packet is enabled. setting is made to determine whether the multi-speed concatenation transmission of isochronous packet is enabled or not. transmission of multi-speed concatenation is valid at the time of isomode transmission in normal mode. in the auto-mode transmission, no function of multi-speed concatenation is supported. even when the reversal data for a phy control packet are different, this phy control packet is not stored in the arf buffer. bit 4 ensnoop : enable snoop bit (rw- initial value: 0b) 0 = normally, only the packet mapped in this node address is received. 1 = snoop mode assumed. regardless of the node address assumed, a snoop mode is set up so that all packets carried on the serial bus, can be received. when a packet is received, the ack code is not returned. all packets received in this mode are stored in the irf buffer. bit 5 rxselfid : receive self id bit (rw- initial value: 1b) 0 = no selfid packet is inserted in the buffer. 1 = selfid packet is input in the buffer. this bit makes setting to decide whether the selfid packet received in the self id phase after bus reset should be put in the buffer area for reception async. 76543210 rxphypkt rxselfid ensnoop multi enacc 15 14 13 12 11 10 9 8 writepending busyctrl 23 22 21 20 19 18 17 16 31 30 29 28 27 26 25 24
MD8412B 16 fujifuilm microdevices co., ltd. ver 1.10 bit6 rxphypkt : receive phy packet bit (rw -initial value: 0b) 0 = phy packet isn?t stored in the buffer. 1 = phy packet is stored in the buffer. it is configured by this bit whether it isn?t put if received phy control packet is put in the buffer area for the reception. when the phy received pingpacket has more than 4 port, that selfid packet isn?t stored in the arf buffer. and, that phy control packet isn?t stored in the arf buffer when the invert data of the phy control packet is different. bit 10~8 busyctrl : busy control bit (rw- initial value: 000b) 000 = a busy acknowledge is returned according to the dual phase retry protocol only if there is no vacancy of one packet to be received at the internal async reception buffer. 001 = an acknowledge is returned in busya status only if there is no vacancy of one packet to be received at the internal async reception buffer. 010 = an acknowledge is returned in busyb status only if there is no vacancy of one packet to be received at the internal async reception buffer. 011 = an acknowledge is returned in busyx status only if there is no vacancy of one packet to be received at the internal async reception buffer. 100 = a busy acknowledge is returned according to the dual phase retry protocol irrespective of whether there is vacancy of one packet to be received at the internal async reception buffer. 101 = an acknowledge is returned in busya status for all packets received irrespective of whether there is vacancy of one packet to be received at the internal async reception buffer. 110 = an acknowledge is returned in busyb status for all packets received irrespective of whether there is vacancy of one packet to be received at the internal async reception buffer. 111 = an acknowledge is returned in busyx status for all packets received irrespective of whether there is vacancy of one packet to be received at the internal async reception buffer. when the MD8412B node is of inbound and a busy status acknowledge is returned for the packet from the outbound node transmitted to MD8412B, contents of that status are set in this register. bit 12 writepending : write request ack-pending bit (rw- initial value: 1b) 0 = ack-complete is returned when reception is normal with ack code for write request packet. 1 = ack-pending is returned when reception is normal with ack code for write request packet. when a write request packet is normally received, the ack code generally returns ack-complete. if the packet cannot be received normally, due to lack of buffer capacity or the like, ack-busy is returned. when this bit is set at "1" the ack code returns ack-pending under the condition that reception is normal. in other words, split transaction of write request is to be executed. upon completion of write request processing, the host is required to transmit a write response packet. the table below shows types of ack codes to be sent back for each packet. items mark by o are ack codes.
MD8412B ver 1.10 fujifuilm microdevices co., ltd. 17 3-2-8 diagnostic status register index 1ch initial value 0000 0000h (read-only register) it is possible to know various status information in this register. bit 2 busystate : busy state bit (r- initial value: 0b) 0 = acknowledge is returned with busya 1 = acknowledge is returned with busyb when busy acknowledge is to be issued at the next opportunity, this node indicates the type of this acknowledge. bit 11~8 atack : at ack bit (r- initial value: 0000b) 0000 = no ack 0001 = ack_complete 0010 = ack_pending 0011 = reserved 0100 = ack_busy_x 0101 = ack_busy_a packet writepending = '0b' writepending = '1b' ack_complete ack_pending ack_busy ack_complete ack_pending ack_busy write request o - o - o o read request - o o - o o write response o - o o - o read response o - o o - o lock request - o o - o o lock response o - o o - o 76543210 busystate 15 14 13 12 11 10 9 8 retrytimemax ackstatus atack 23 22 21 20 19 18 17 16 31 30 29 28 27 26 25 24 itbusy atbusy
MD8412B 18 fujifuilm microdevices co., ltd. ver 1.10 0110 = ack_busy_b 0111~1100 = reserve 1101 = ack_data_error 1110 = ack_type_error 1111 = reserve for the packet sent from the transmitter during transmission, contents of acknowledge (ack code) returned from the destination node are reflected in this register. the reflection timing is when a busy flag for showing the packet being processed in the transmitting asynchronous buffer is negated. this value is held until this busy is negated for the next packet transmission. bit 13~12 ackstatus : ack status bit (r- initial value: 00b) 00 = normal reception 01 = parity error 10 = packet lost (indicating that no acknowledge packet has been sent in the specified time) 11 = reserve for the transmitted asynchronous packet, the status of acknowledge packet returned from the destination node is indicated. bit 15 retrytimemax : retry time max bit (r- initial value: 0b) 0= normal 1 = max. number of retries this bit is used to indicate the situation in regard to the maximum number of retries for the retry count setting in the atretry register at the beginning of a certain retry phase. whether the said retry phase has been finished or is still busy at that time can be identified with the atack bit. this value is maintained until the next packet transmission is carried out. bit 24 atbusy : at busy bit (r- initial value: 0b) 0 = indicates that atgo issuing is possible. 1 = indicates that atgo issuing is impossible, and that a packet is presently being processed for the pre- viously issued atgo. this bit is asserted upon the issuing of atgo for asynchronous transmission. it is negated when return of this acknowledge has been set in the atack register. the host cannot issue the next atgo while this bit is being asserted. even though it is attempted, it is disregarded. when a packet transmission turns to be a retry operation, this bit is never negated until the said retry is finished. bit 25 itbusy : it busy bit (r- initial value: 0b) 0 = indicates that itgo issuing is possible. 1 = indicates that itgo issuing is impossible, and that a packet is presently being processed for the previ- ously issued itgo. for isochronous transmission in normal isomode, this bit is asserted with itgo issued, and negated upon completion of packet transmission. the host cannot issue the next itgo until this bit is being asserted. even though it is attempted, it is disregarded.
MD8412B ver 1.10 fujifuilm microdevices co., ltd. 19 3-2-9 phy control register index 20h initial value 0000 0000h using this register, a register in phy chip is accessed. when reading a certain register, its register address is set in the regaddr register and the rdreg bit is made active. with the rdreg bit being active, a read request for the addressed reg- ister is made to the phy chip and the rdreg bit is then cleared. contents of the addressed register from the phy chip are entered in the regdata register. the write request to the phy register for the data in the regdata register is also made by triggering the wrreg bit of the phy address set in the regaddr register. bit 7~0 regdata : register data bit (rw- initial value: 00h) with a write request, data being transferred to phy are stored. with read request also, data transferred from phy are stored. when reading out the contents of this register, contents of regdata are read out, the value taken from phy with the previous read request. in other words, the value taken from the host cannot be directly read out. to read out, a read request must be sent to phy. bit 11~8 regaddr : register address bit (rw- initial value: 00h) the address value of phy being accessed is set. bit 12 wrreg : write register bit (rw- initial value: 0b) 0 = normal condition 1 = write request issued a write request is issued toward the phy register. after this write request, this bit is cleared. bit 13 rdreg : read register bit (rw- initial value: 0b) 0 = normal condition 1 = read request issued a read request is issued toward the phy register. after this read request, this bit is cleared. bit 14 regrcvd : register data received bit (rw- initial value: 0b) 0 = normal condition 1 = indicating that data from phy have been stored in regdata after the issuing of read request after a read request has been issued toward the phy register, "1" set upon the storage of phy data in reg- data. since then, "1" signal for testing. cleared to "0" when reading is attempted once from this register. 76543210 regdata 15 14 13 12 11 10 9 8 regrcvd rdreg wrreg regaddr 23 22 21 20 19 18 17 16 31 30 29 28 27 26 25 24
MD8412B 20 fujifuilm microdevices co., ltd. ver 1.10 3-2-10 atretries register index 24h initial value 0000 0001h there is a function of performing automatic retry when asynchronous packet transmission is attempted by the MD8412B node and busy acknowledge is returned from this destination node. the number of retries is set in this register. once a retry phase is assumed, a busy flag of the atgo register is never negated until any acknowledge other than busy is returned from the destination node or the preset number of retries is attained. in this state, the next packet transmission is disabled. bit 3~0 maxretrycount : maximum retry count bit (rw- initial value: 01h) this register sets up the maximum number of retries for busy acknowledge from the destination node. if the retry phase is not completed within this set value, a retry time-out status flag is given in the atack register to complete the retry phase attempted by the MD8412B. since then, packet data are flushed within the atf buffer. the maximum number that can be set is 15. when "0000" is set, the MD8412B does not assume a retry phase automatically. in this case, packet data are flushed for busy acknowledge. when an error acknowledge is returned in the retry phase, retry is suspended at that time point and contents of the buffer are flushed. further operation is halted by presenting a flag (ackerr). bit 7~4 retrycount : retry count bit (r- initial value: 00h) the number of present retries is indicated in the middle of a retry attempted from MD8412B. bit 8 retrystop : retry stop bit (rw- initial value: 0b) when the MD8412B automatically assumes the retry phase and the limit value is not attained yet during this retry action, this bit is used to perform the forced end of this retry. when this bit is set at "1", it is automatically cleared after the completion of the retry phase. 0: normal condition 1: forced end 76543210 retrycount maxretrycount 15 14 13 12 11 10 9 8 retrystop 23 22 21 20 19 18 17 16 31 30 29 28 27 26 25 24
MD8412B ver 1.10 fujifuilm microdevices co., ltd. 21 3-2-11 cycle timer register index 28h initial value 0000 0000h the present cycle timer value is indicated. as described below, this register is divided into three areas. when the node employing MD8412B is of cyclemaster and a cycle start packet is being transmitted, this register value is loaded. in other- wise case, the cycle timer value in the received cycle start packet is loaded in this register in order to update the cycle tim er. timing to load is when the lo byte of cycleoffset has been written. bit 11~0 cycleoffset : cycle offset bit (rw- initial value: 00h) this area is used for counting up with a 24.576mhz clock. it is actuated with modulo3072. bit 24 cyclecount : cycle count bit (rw- initial value: 00h) this area is used for counting up when the cyclefield register carries to count isochronous cycles. it is actu- ated with modulo8000. bit 31~25 cycleseconds : cycle seconds bit (rw- initial value: 00h) this area is used for counting up when the cyclecount register carries to count seconds. it is actuated with modulo128. 76543210 cycleoffset 15 14 13 12 11 10 9 8 cyclecount cycleoffset 23 22 21 20 19 18 17 16 cyclecount 31 30 29 28 27 26 25 24 cycleseconds cyclecount
MD8412B 22 fujifuilm microdevices co., ltd. ver 1.10 3-2-12 isochronous packet length register index 2ch initial value 0004 0000h when isomode is assumed and its transmission mode is auto (setting value = "010b" or "100b", the data volume of one packet to be transferred in each isochronous cycle is set in this register. bit 27~16 itlength : isochronous transmit length bit (rw- initial value: 04h) length of a packet being transmitted is set in this register. during transmission, this value is used at the header part. 3-2-13 isochronous configuration register 1,2,3,4 index 30h, 34h, 38h, 3ch initial value 0000 0000h for transmission/reception of an isochronous packet, this register group determines how MD8412B handles this packet. in some cases, registers are not used according to the number of registers by isomode setting nor the definition in each reg- ister. 76543210 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 itlength 31 30 29 28 27 26 25 24 itlength 76543210 stopsync isorxen syncen 15 14 13 12 11 10 9 8 sync startsync 23 22 21 20 19 18 17 16 speed 31 30 29 28 27 26 25 24 ta g channel
MD8412B ver 1.10 fujifuilm microdevices co., ltd. 23 bit 0 syncen : sync enable bit (rw- initial value: 0b) 0 = packet transmission/reception is effected regardless of the contents of startsync and stopsync. dur- ing automode transmission, contents of the sync register are reflected at any time in the sync area of the packet header. 1 = in the receive mode, packet reception is controlled with the channel number of the above setting plus startsync and stopsync. during automode transmission, contents of start sync are entered in the sync field of the packet header to be transmitted shortly after the itstart terminal or the itstart register has been turned active. since then, contents of sync are entered in stopsync shortly after itstart is turned non-active. bit 1 isorxen : isochronous receive enable bit (rw- initial value: 0b) 0 = isochronous reception disabled 1 = isochronous reception enabled setting is made to define whether isochronous reception is enabled or not. bit 7~4 stopsync : stop sync bit (rw- initial value: 00h) when syncen=1, reception control is effected with the sync field values of this bit and packet. once packet reception is started with startsync and after a packet has been received, with which its register value coincides with the sync field of a packet of the set channel number, packet reception is suspended thereafter. when syn- cen="1b" in the auto-transmission mode, and if transmission is stopped by the itstart terminal or the itstart register, this value is written in the sync field of the last packet received shortly before stoppage. bit 8~11 startsync : start sync bit (rw- initial value: 00h) when syncen=1, reception control is effected with the sync field value of this bit and packet. reception is started again with a packet whose register value coincides with the sync field value of the packet with the preset channel number. when syncen="1b" the auto-transmission mode, and when transmission is started with the itstart terminal or the itstart register, this value is written in the sync field of the packet to be sent first. bit 15~12 sync : sync bit (rw- initial value: 00h) for "010b" and "100b" in isomode, in the isochronous transmission auto-mode, this register sets up a value so that the MD8412B can input this value in the sync field of the packet header. in other modes, this register remains to be disabled. with syncen="0b" this value is written at any time. when syncen="1b" this value is written in a packet other than the start/end packet, with the itstart terminal or the itstart register. bit 17~16 speed : speed bit (rw- initial value: 00b) 00 = transmission at 100mbps 01 = transmission at 200mbps 10 = transmission at 400mbps 11 = reserved in the transmission mode, the transfer speed is set up for transmission to be effected over the cable. in the reception mode, this register remains to be disabled. bit 29~24 channel : channel bit (rw- initial value: 00h) in auto-transmission mode, a channel is specified for the isochronous packet. the channel number set here is loaded in the packet header for transmission. in the reception mode, an isochronous channel intended for recep- tion in both modes is set up. the setting range is from 0 to 63. bit 31~30 tag : tag bit (rw- initial value: 00h) in auto-transmission mode, a tag is specified for an isochronous packet. the setting range is from 0 to 3. the relationship between contents of the isomode register and this configuration register group is shown below.
MD8412B 24 fujifuilm microdevices co., ltd. ver 1.10 mode icr number transmit/receive tag channel speed syncen sync start sync stop sync 000 - normal transmit - - - - - - - 1, 2, 3, 4 normal receive valid valid - valid - valid valid 001 - normal transmit - - - - - - - 2 auto receive valid valid - valid - valid valid 3, 4 (unused) 010 1 auto transmit valid valid valid valid valid valid valid 2, 3, 4 normal receive valid valid - valid - valid valid 011 2, 3 auto receive valid valid - valid - valid valid 1, 4 (unused) 100 1 auto transmit valid valid valid valid valid valid valid 2 auto receive valid valid - valid - valid valid 3, 4 (unused) 101 1, 2, 3, 4 normal receive valid valid - valid - valid valid *icr: isochronous configuration register
MD8412B ver 1.10 fujifuilm microdevices co., ltd. 25 3-2-14 atf data register index 40h initial value 0000 0000h this is a register for writing asynchronous packet transmission data. data are written in the internal buffer for asynchro- nous transmission. in cases other than host 32-bit access, it is always necessary to write data in the quadlet unit. 3-2-15 arf data register index 44h initial value 0000 0000h this is a register for reading asynchronous packet reception data. data are read from the internal buffer for asynchronous reception. in cases other than host 32-bit access, it is always necessary to read data in the quadlet unit. 76543210 atfdata 15 14 13 12 11 10 9 8 atfdata 23 22 21 20 19 18 17 16 atfdata 31 30 29 28 27 26 25 24 atfdata 76543210 arfdata 15 14 13 12 11 10 9 8 arfdata 23 22 21 20 19 18 17 16 arfdata 31 30 29 28 27 26 25 24 arfdata
MD8412B 26 fujifuilm microdevices co., ltd. ver 1.10 3-2-16 itf/irf data register index 48h initial value 0000 0000h in cases other than "011b" in isomode, this register is used for isochronous transmission data writing. data are written in the internal buffer for isochronous transmission. in the case of "011b" this register is used for isochronous reception data reading and data are read from the internal buffer for asynchronous reception. in cases other than host 32-bit access, it is always necessary to write data in the quadlet unit. when isomode="011b" this register is used for a packet to be set by the isochronous configuration register-2. resetitf/irf is used when resetting the internal reception buffer from which data are read. 3-2-17 irf data register index 4ch initial value 0000 0000h this register is used for isochronous reception data read-out. data are read from the internal buffer for asynchronous reception. in cases other than host 32-bit access, it is always necessary to write data in the quadlet unit. when iso- mode="011b" this register is used for a packet to be set by the isochronous configuration register-3. resetirf is used when resetting the internal reception buffer from which data are read. 76543210 itf/irfdata 15 14 13 12 11 10 9 8 itf/irfdata 23 22 21 20 19 18 17 16 itf/irfdata 31 30 29 28 27 26 25 24 itf/irfdata 76543210 irfdata 15 14 13 12 11 10 9 8 irfdata 23 22 21 20 19 18 17 16 irfdata 31 30 29 28 27 26 25 24 irfdata
MD8412B ver 1.10 fujifuilm microdevices co., ltd. 27 3-2-18 buffer status and control register index 50h initial value 0000 0055h this register is used for asynchronous transmission/ reception. it is used for the status control of internal buffer for isoch- ronous transmission/reception and for the flush control for an asynchronous reception buffer. bit 0 atfempty : atf empty bit (r- initial value: 1b) 0 = indicating a condition that the buffer is not empty 1 = indicating a condition that the buffer is empty this bit indicates that the asynchronous transmission buffer being accessed from the atfdata register is empty. bit 1 atffull : atf full bit (r- initial value: 0b) 0 = indicating a condition that the buffer is not full 1 = indicating a condition that the buffer is full this bit indicates that the asynchronous transmission buffer being accessed from the atf data register is full. bit 2 arfempty : arf empty bit (r- initial value: 1b) 0 = indicating a condition that the buffer is not empty 1 = indicating a condition that the buffer is empty this bit indicates that the asynchronous reception buffer being accessed from the arf data register is empty. bit 4 itf/irfempty : i tf/irf empty bit (r- initial value: 1b) 0 = indicating a condition that the buffer is not completely empty 1 = indicating a condition that the buffer is completely empty this bit is used for transmission in isomode in cases other than ??11b?m it is also used for reception in the case of ??11b?m it indicates that the isochronous buffer being accessed from the itf/irf data register is empty. bit 5 itf/irffull : itf/irf full bit (r- initial value: 0b) 0 = indicating a condition that the buffer is not full 1 = indicating a condition that the buffer is full 76543210 irfempty itf/irf full itf/irf empty arfempty atffull atfempty 15 14 13 12 11 10 9 8 selectdreq dreqen 23 22 21 20 19 18 17 16 irfcount 31 30 29 28 27 26 25 24 irfcount
MD8412B 28 fujifuilm microdevices co., ltd. ver 1.10 this bit is used for transmission in isomode in cases other than ??11b?m it is also used for reception in the case of "011b". it indicates that the isochronous buffer being accessed from the itf/irf data register is full. bit 6 irfempty : irf empty bit (r- initial value: 1b) 0 = indicating a condition that the buffer is not empty 1 = indicating a condition that the buffer is empty bit 12 dreqen : dreq enable bit (rw- initial value: 0b) 0 = dreq signal is left non-active at any time 1 = dreq signal is turned active as the status of contents chosen by selectdreq. this bit is intended to make the dreq signal valid. bit 14~13 selectdreq : select dreq bit (rw- initial value: 00b) 00 = this bit is reflected on the dreq signal as the status being equivalent to that of the atffull bit for the buffer being accessed by the atf data register. 01 = this bit is reflected on the dreq signal as the status being equivalent to that of the atfempty bit for the buffer being accessed by the atf data register. 10 = this bit is reflected on the dreq signal as the status being equivalent to that of the itffull bit in the transmission mode and that of irfempty bit in the reception mode, for the buffer being accessed by the itf/irf data register. 11 = this bit is reflected on the dreq signal as the status being equivalent to that of the irfempty bit for the buffer being accessed by the irf data register. this register is used to determine what buffer status in the chip should be reflected on the dreq signal. bit 24~16 irfcount : irf count bit (r- initial value: 00b) this bit is used to indicate the data size in the quadlet unit, stored in the buffer (irf or itf/irf) chosen by the selectdreq bit in the auto-mode. invalid if selectdreq is 00,01. if the first setting is made for selectdreq or it is modified after the power supply has been turned on, it is nec- essary to follow the procedures specified below, in order to read out the irfcount data. 1. set at dreqen = "0" 2. selectdreq is set for the required fifo type. 3. after the completion of the above-mentioned setting, the data size stored in the required fifo can be read from the irfcount.
MD8412B ver 1.10 fujifuilm microdevices co., ltd. 29 3-2-19 interrupt register index 54h initial value 0000 0000h by reading out data from this register, the host can know a variety of interrupt factors in MD8412B. all bits in this regis- ter indicate with "1" an interrupt factor has arisen. bit 3 cmdreset : command reset bit (rw- initial value: 0b) this bit is set at "1" when a packet is received, addressed to the reset area in the csr space. bit 4 cyclelost : cycle lost bit (rw- initial value: 0b) if the MD8412B node is not of the cycle master, this bit is set at "1" when a cyclestart packet is received and the internal cycle timer is updated, but the next cyclestart packet cannot be received in 250?ec by that cycle timer. bit 5 cycledone : cycle done bit (rw- initial value: 0b) set at "1" when a certain isochronous cycle is over. bit 6 cyclestart : cycle start bit (rw- initial value: 0b) set at "1" when a new isochronous cycle is started. bit 7 cycleseconds : cycle seconds bit (rw- initial value: 0b) set at "1" when a cycle timer possessed by MD8412B has counted 1 second. bit 8 sentrej : sent reject bit (rw- initial value: 0b) set at "1" when an asynchronous packet is received, but this packet cannot be completely received because of lack of a vacant space enough to accommodate the packet capacity in the receiving buffer, and a busy acknowl- edge packet is returned from MD8412B to the source node. bit 9 hdrerr : header error bit (rw- initial value: 0b) set at "1" during reception of a packet, if the received packet contains an error header. in such a case, in iso- chronous reception, data transfer to that receiving buffer is not performed and this packet is canceled. bit 10 tcodeerr : tcode error bit (rw- initial value: 0b) set at "1" during transmission of a packet, if a code not supported by MD8412B is set in the tcode area of the packet header. 76543210 cycleseconds cyclestart cycledone cyclelost cmdreset 15 14 13 12 11 10 9 8 phyint busreset busresetfin phyregrcvd ackerr tcodeerr hdrerr sentrej 23 22 21 20 19 18 17 16 atxend irfrxend itf/irf rxend arxend itxend itfnotx irfflush itf/irf flush 31 30 29 28 27 26 25 24 arfflush
MD8412B 30 fujifuilm microdevices co., ltd. ver 1.10 bit 11 ackerr : ack error bit (rw- initial value: 0b) set at "1" for a transmitted asynchronous packet, if an acknowledge packet returned from the destination node cannot be normally received. bit 12 phyregrcvd : phy register received bit (rw- initial value: 0b) set at "1" when data from phy are stored in regdata after the issuing of a read request toward the phy reg- ister. bit 13 busresetfin : bus reset finish bit (rw- initial value: 0b) this bit is set at "1" when bus reset is finished and subactiongap is detected. bit 14 busreset : bus reset bit (rw- initial value: 0b) set at "1" when phy is turned in bus reset mode. bit 15 phyint : phy interrupt bit (rw- initial value: 0b) set at "1" when an interrupt factor is sent from phy connected to MD8412B. bit 16itf/irfflush: itf/irf flush bit (rw- initial value: 0b) set at "1" when MD8412B makes isochronous reception, but a packet routed to the ift/irf buffer cannot be normally received for the following reasons, thus causing the received data canceled: bit 17 irfflush : irf flush bit (rw- initial value: 0b) set at "1" when MD8412B makes isochronous reception, but a packet routed to the irf buffer cannot be nor- mally received for the following reasons, thus causing the received data canceled: bit 18 itnotx : isochronous no transmit bit (rw- initial value: 0b) set at "1" during isochronous transmission by MD8412B in auto-mode, if this transmission cannot be accom- plished after reception of the cycle start packet. bit 19 itxend : isochronous transmit end bit (rw- initial value: 0b) set at "1" when isochronous transmission is attempted by MD8412B in normal mode, and a group of packets has been completely transferred for different channels required to be transferred by itgo. bit 20 arxend : asynchronous receive end bit (rw- initial value: 0b) set at "1" when asynchronous reception is performed by MD8412B and data are stored in the arf buffer. bit 21 itf/irfrxend : isochronous receive end (itf/irf) bit (rw- initial value: 0b) set at "1" when isochronous reception is performed by MD8412B and data are stored in the ift/irf buffer. bit 22 irfrxend : isochronous receive end (irf) bit (rw- initial value: 0b) set at "1" when isochronous reception is performed by MD8412B and data are stored in the irf buffer. bit 23 atxend : asynchronous transmit end bit (rw- initial value: 0b) set at "1" when asynchronous transmission is performed by MD8412B and an ack code returned from the destination is received upon completion of transmission operation. this bit is also set at "1" when retry opera- tion is performed and its retry phase is completed, or when ackerr is set in the middle of operation. bit 24 arfflush : arf flush bit (rw- initial value: 0b) when the MD8412B performs asynchronous reception and the packet routed to the arf buffer cannot be received normally for the reasons specified below, this bit is set at "1" if the received data are flushed as a result.
MD8412B ver 1.10 fujifuilm microdevices co., ltd. 31 - the asynchronous reception buffer has no vacant area to accommodate the required amount of data for the received packet. - the packet header and the payload domain involve a crc error. - the data length set value in the packet header does not coincide with the amount of data in the payload domain. 3-2-20 interrupt mask register index 58h initial value 0000 0000h when each interrupt factor in the interrupt register need not be reflected on the int# signal, it is masked by this register. arrangements of this register are the same as those for the interrupt register. each bit is masked by setting at "1". 3-2-21 tgo register index 5ch initial value 0000 0000h for transmission of an asynchronous packet and transmission of an isochronous packet in normal isomode, "1" is set at the tgo register in this register to inform the MD8412B of packet transmission. the host transmits the sending packet to the internal buffer of MD8412B, and then sets up this tgo register. with "1" of this tgo register, the MD8412B begins to send a packet, assuming that one packet consists of data written in the buffer by then. in isochronous transmission, how- ever, actual transmission of data begins with cyclestart shortly after the issuing of itgo. according to the go command issued, the atbusy bit is turned "1" or asynchronous transmission and the itbusy bit is turned "1" for isochronous trans- mission. by this operation, the host can identify that the MD8412B has started transmission operation. the timing to per- mit the next tgo issuing is after the atbusy bit is turned "0" for asynchronous transmission and the itbusy bit is turned "0" for isochronous transmission. even when tgo is issued while atbusy or itbusy is "1" the MD8412B disregards it. even when "0" is written in this register, such an attempt is invalid. bit 0 atgo : at go bit (rw- initial value: 0b) by writing "1" in this register, the MD8412B is informed of the start of asynchronous packet transmission. bit 1 itgo : it go bit (rw- initial value: 0b) by writing "1" in this register, the MD8412B is informed of the start of isochronous packet transmission. this bit is valid only if isomode is normal. 76543210 itstart itgo atgo 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 31 30 29 28 27 26 25 24
MD8412B 32 fujifuilm microdevices co., ltd. ver 1.10 bit 2 itstart : it start bit (rw- initial value: 0b) by writing "1" in this register, the MD8412B is informed of the start of isochronous packet transmission in auto-mode. by writing "0" therein, the MD8412B can know the stoppage of operation. this bit is valid only if isomode is auto. the relationship with the itstart signal terminal is logical or. 3-2-22 bus time register index 60h initial value 0000 0000h this is the timer register used to count the bus time in the 32-bit width. the bus time is counted up each time the cyclecount timer of the cycletime register is carried up. it can be used as the bus_time register for the serial-dependent registers of ieee1212. bit 6~0 secondcountlo : bus time l bit (r- initial value: 0000000h) this is lower 7 bit of bus time register. it coincides with the value of cycletimesecond. bit 31~7 secondcounthi : but time h bit (rw - initial value: 0h) this is upper 25 bit of bus time register. index 64h initial value 0000 0000h this address is reserved. 76543210 second counthi secondcountlo 15 14 13 12 11 10 9 8 secondcounthi 23 22 21 20 19 18 17 16 secondcounthi 31 30 29 28 27 26 25 24 secondcounthi 76543210 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 31 30 29 28 27 26 25 24
MD8412B ver 1.10 fujifuilm microdevices co., ltd. 33 3-2-23 atretries register index 68h initial value 00c8 0000h when an asynchronous packet is transmitted from the node of the MD8412B and a busy acknowledge signal is returned from the destination node, the MD8412B automatically functions to make a retry action. the number of retries and the time are set in this register. once in the retry phase, the busy flag of the atgo register is never negated until an acknowl- edge signal other than busy is returned from the destination node or the preset number of retries and time are exceeded. therefore, the next packet transmission is impossible in this state. it is, however, possible to perform the forced ending of the retry phase if the retrystop bit is used. this register is used to set up the duration of a retry upon the reception of a busy acknowledge signal sent from the desti- nation node. the retry phase used to see this register value is the dual phase. if the retry phase cannot be finished within th e preset time period, the retry time-out status flag is presented in the atack register to complete the retry phase that is to be executed by the MD8412B. since then, the packet data in the atf buffer are flushed. the maximum value that can be set is within 8 seconds. if "0" is set in this field, the MD8412B automatically sets itself not to perform a dual phase retry. in such a case, the packet data to the busy acknowledge signal are flushed. also, when an error acknowledge signal is returned in the middle of a retry phase, this retry is suspended at that time point and the buffer is flushed to complete the retry by presenting a flag (ackerr). bit 12~0 retrycyclelimit : retry cycle limit bit (r- initial value: 0000h) in the dual retry phase, the MD8412B indicates the present retry lapse time in the cycle unit. bit 15~13 retrysecond/limit : retry second limit bit (r-initial value: 0h) in the dual retry phase, the MD8412B indicates the present retry lapse time in the second unit. bit 16~28 maxretrycyclelimit : maximum retry cycle limit bit (rw- initial value: 00c8h) this area is used for the specified values in the cycle unit. it is effective within the range of 0 to 7999. bit 29~31 maxretrysecondlimit : maximum retry second limit bit (rw- initial value: 0000h) this area is used for the specified valued in the second unit. 76543210 retrycyclelimit 15 14 13 12 11 10 9 8 retrysecondlimit retrycyclelimit 23 22 21 20 19 18 17 16 maxretrycyclelimit 31 30 29 28 27 26 25 24 maxretrycyclelimit retrycyclelimit
MD8412B 34 fujifuilm microdevices co., ltd. ver 1.10 3-3 registers register adrs 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 version 00h version revision control 04h dmawidth little isomode cyclesource cyclemaster cycletimeren fora lpson receiveen transmiten node identification 08h idvalid busnumber nodenumber reset 0ch resetdma resetlink resettrans resetirf resetarf resetitf/irf resetatf asynchronous 10h arcvbuffersize atotalsize isochronous 14h ircvbuffersize itotalsize packet control 18h writepending busyctrl rxphypkt rxselfid ensnoop multi enacc diagnostic status 1ch itbusy atbusy retrytimemax ack status atack busystate phy control 20h regrcvd rdreg wrreg regaddr regdata atretries 24h retrystop retrycount maxretrycount cycle timer 28h cycleseconds cyclecount cycleoffset bandwidth control 2ch itlength isochronous configuration 1 30h tag channel speed sync startsync stopsync isorxen syncen isochronous configuration 2 34h tag channel speed sync startsync stopsync isorxen syncen table 3-3-1 registers 1
MD8412B ver 1.10 fujifuilm microdevices co., ltd. 35 register adrs 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 isochronous configuration 3 38h tag channel speed sync startsync stopsync isorxen syncen isochronous configuration 4 3ch tag channel speed sync startsync stopsync isorxen syncen atf data 40h atf data arf data 44h arf data itf/irf data 48h itf/irf data irf data 4ch irf data buffer status and control 50h irfcount selectdreq dreqen irfempty itf/irfempty itf/irfempty arfempty atffull atfempty interrupt 54h arfflush atxend irfrxend itf/irfrxend arxend itxend itnotx irfflush itf/irfflush phyint busreset busresetfin phyregrcvd ackerr tcodeerr hdrerr sentrej cycleseconds cyclestart cycledone cyclelost cmdreset interrupt mask 58h arfflush atxend irfrxend itf/irfrxend arxend itxend itnotx irfflush itf/irfflush phyint busreset busresetfin phyregrcvd ackerr tcodeerr hdrerr sentrej cycleseconds cyclestart cycledone cyclelost cmdreset tgo 5ch itstart itgo atgo bus time 60h secondcounthi secondcountlo reserved 64h at retries 68h maxretry secondlimit maxreteycyclelimit retry secondlimit reteycyclelimit table 3-3-2 registers 2
MD8412B 36 fujifuilm microdevices co., ltd. ver 1.10 4 data format 4-1 asynchronous 4-1-1 quadlet transmit busid : bus id field this field is used to select the busid that has been set in the source area of the header area in the ieee1394 packet format, in order to determine whether register setting of the MD8412B should be made valid or 3ff fixed. 0 = busid is selected to make the set value valid in the MD8412B register. 1 = busid is made 3ff fixed. when this bit is set at 1, the busid register setting becomes invalid in the MD8412B. spd : speed field this field is used to designate the transfer speed. refer to table 4-6-6 regarding setting values. tlabel : transaction label field this field is used to define a unique tag for each transferred transaction. the tlabel sent for requesting is used as a transaction label for correct response. the values used are valid in the range of 0h~fh. rt : retry field this field is used to define whether this packet is in the middle of making a retry. the retry protocol is fol- lowed by the destination node. refer to table 4-6-1 regarding setting values. tcode : transaction code field this field is used to set up a transaction code. the transaction code is used to define the packet type. refer to table 4-6-2 regarding setting values. priority : priority field this field is valid in the back plane environment. therefore, the MD8412B is required to set up 0000b, with- out fail. destinationid : destination idfield this field is used to set up destination bus and node id. the upper 10 bits out of the length of 16 bits are used to set up the destination bus id and the lower 6 bits are used to set up the destination physical id. some figures in the setting value may have special meanings. refer to table 4-6-3 regarding details. 313029282726252423222120191817161514131211109876543210 busid spd tlabel rt tcode priority destinationid destinationoffset_h destinationoffset_l quadlet data (for write request and read response) table 4-1-1 quadlet transmit format (asynchronous)
MD8412B ver 1.10 fujifuilm microdevices co., ltd. 37 destinationoffset : destination offset address field this field is used to define the lower 48-bit address of the destination node for the requested packet. the set- ting value need be defined in the quadlet unit in the case of a read request for quadlet data and a write request for quadlet data.) quadletdata : quadlet data field this field is used to set up actual transfer data (1 quadlet). 4-1-2 block transmit busid : bus id field this field is used to select the busid that has been set in the source area of the header area in the ieee1394 packet format, in order to determine whether register setting of the MD8412B should be made valid or 3ff fixed. 0 = busid is selected to make the set value valid in the MD8412B register. 1 = busid is made 3ff fixed. when this bit is set at 1, the busid register setting becomes invalid in the MD8412B. spd : speed field this field is used to designate the transfer speed. refer to table 4-6-6 regarding setting values. tlabel : transaction label field this field is used to define a unique tag for each transferred transaction. the tlabel sent for requesting is used as a transaction label for correct response. the values used are valid in the range of 0h~fff. rt : retry field this field is used to define whether this packet is in the middle of making a retry. the retry protocol is fol- lowed by the destination node. refer to table 4-6-1 regarding setting values. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 busid spd tlabel rt tcode priority destinationid destinationoffset_h destinationoffset_l datalength extended_tcode block data quadlet 1 other block data quadlets padding (if nacessary) table 4-1-2 block transmit format (asynchronous)
MD8412B 38 fujifuilm microdevices co., ltd. ver 1.10 tcode : transaction code field this field is used to set up a transaction code. the transaction code is used to define the packet type. refer to table 4-6-2 regarding setting values. priorty : priority field this field is valid in the back plane environment. therefore, the MD8412B is required to set up 0000b, with- out fail. destinationid : destination id field this field is used to set up destination bus and node id. the upper 10 bits out of the length of 16 bits are used to set up the destination bus id and the lower 6 bits are used to set up the destination physical id. some figures in the setting value may have special meanings. refer to table 4-6-3 regarding details. destinationoffset : destination offset address field this field is used to define the lower 48-bit address of the destination node for the requested packet. the set- ting value need be defined in the quadlet unit in the case of a read request for quadlet data and a write request for quadlet data. datalength : data length field this field is used to set up data length for the blockdata field. the maximum value of the setting value depends on that of the speed field. refer to table 4-6-4 regarding details. extended_tcode : extended transaction code field this field is used to define the extension tcode. this extended_tcode becomes valid only if tcode is "lock request" or "lock response" for other tcodes, 0000h must be set in this register. refer to table 4-6-5 regarding details. blockdat : block data field this field is used to set up actual transfer data. if the datalength field is not defined with a multiple of 4, this field is required to be completed so that the quadlet unit is finished with 00h. 4-1-3 quadlet receive 313029282726252423222120191817161514131211109876543210 destinationid tlabel rt tcode priority sourceid destinationoffset_h destinationoffset_l quadlet data (for write request and read response) spd acksent table 4-1-3 quadlet receive format (asynchronous)
MD8412B ver 1.10 fujifuilm microdevices co., ltd. 39 destinationid : destination id field the destination bus of this packet and the node id are saved in this field. the upper 10 bits out of the length of 16 bits are used to set up the destination bus id and the lower 6 bits are used to set up the destination physical id. some figures in the setting value may have special meanings. refer to table 4-6-3 regarding details. tlabel : transaction label field this field is used to define a unique tag for each transferred transaction. rt : retry field this field is used to define whether this packet having been sent is in the middle of making a retry. refer to table 4-6-1 regarding setting values. tcode : transaction code field a transaction code is saved in this field. the transaction code is used to define the packet type. refer to table 4-6-2 regarding setting values. priority : priority field this field is valid in the back plane environment. therefore, the MD8412B is required to save 0000b, with- out fail. sourceid : source id field this field is used to save the source bus and node id. the upper 10 bits out of the length of 16 bits are used to set up the destination bus id and the lower 6 bits are used to set up the destination physical id. some figures in the setting value may have special meanings. refer to table 4-6-3 regarding details. destinationoffset : destination offset address field this field is used to save the lower 48-bit address of the destination node for the requested packet. quadletdata : quadlet data field this field is used to save transferred data. spd : speed field this field is used to designate the received speed. refer to table 4-6-6 regarding setting values. acksent : acksent field this field saves the ack code returned as an acknowledge signal after this packet has been received. refer to table 4-6-7 regarding details.
MD8412B 40 fujifuilm microdevices co., ltd. ver 1.10 4-1-4 block receive destinationid : destination id field the destination bus of this packet and the node id are saved in this field. the upper 10 bits out of the length of 16 bits are used to set up the destination bus id and the lower 6 bits are used to set up the destination physical id. some figures in the setting value may have special meanings. refer to table 4-6-3 regarding details. tlabel : transaction label field this field is used to define a unique tag for each transferred transaction. rt : retry field this field is used to define whether this packet having been sent is in the middle of making a retry. refer to table 4-6-1 regarding setting values. tcode : transaction code field a transaction code is saved in this field. the transaction code is used to define the packet type. refer to table 4-6-2 regarding setting values. priorty : priority field this field is valid in the back plane environment. therefore, 0000b is always saved. sourceid : source id field this field is used to save the source bus and node id. the upper 10 bits out of the length of 16 bits are used to set up the destination bus id and the lower 6 bits are used to set up the destination physical id. some figures in the setting value may have special meanings. refer to table 4-6-3 regarding details. destinationoffset : destination offset address field this field is used to save the lower 48-bit address of the destination node for the requested packet. 313029282726252423222120191817161514131211109876543210 destinationid tlabel rt tcode priority sourceid destinationoffset_h destinationoffset_l datalength extended_tcode block data quadlet 1 other block data quadlets spd acksent table 4-1-4 block receive format (asynchronous)
MD8412B ver 1.10 fujifuilm microdevices co., ltd. 41 datalength : data length field this field is used to set up data length for the blockdata field. extended_tcode : extended transaction code field this extended_tcode becomes valid only if tcode is "lock request" or "lock response" for other tcodes, 0000h is saved in this register. blockdata : block data field the transferred data are saved in this field. spd : speed field this field is used to designate the received speed. refer to table 4-6-6 regarding setting values. acksent : acksent field this field saves the ack code returned as an acknowledge signal after this packet has been received. refer to table 4-6-7 regarding details.
MD8412B 42 fujifuilm microdevices co., ltd. ver 1.10 4-2 asynchronous stream 4-2-1 transmit tcode : transaction code field a transaction code is stored in this field. the transaction code is used to define the type of a packet. in this case, the value is required to be 0xa. datalength : data length field this field is used to set up data length for the blockdata field. tag : tag field this field is used to set up tag for asynchronous transmit. channel : channel field this field is used to set up channel number for asynchronous transmit. spd : speed field this field is used to designate the transfer speed. sy : sync field this field is used to set up sync data for asynchronous transmit. asynchronous stream data : asynchronous stream data field this field is used to set up actual transfer data. if the datalength field is not defined with a multiple of 4, this field is required to be completed so that the quadlet unit is finished with 00h. 313029282726252423222120191817161514131211109876543210 spd tcode reserved datalength tag channel sy asynchronous stream data padding (if necessary) table 4-2-1 asynchronous stream transmit format
MD8412B ver 1.10 fujifuilm microdevices co., ltd. 43 4-2-2 receive datalength : data length field this field is used to designate the received data length for the blockdata field. tag : tag field this field is used to designate the received tag data. channel : channel field this field is used to designate the received channel number. sy : sync field this field is used to designate the received sync data. tcode : transaction code field a transaction code is saved in this field. the transaction code values is "ah". asynchronous stream data : asynchronous stream data field the transferred data are saved in this field. spd : speed field a receiving speed is stored in this field. as for the value, refer to table 4-6-6. errcode : error code field an acknowledge signal at the time of reception is stored in this field. unlike the case of asynchronous data transfer, however, no value of this field is returned. for more details, refer to table 4-6-7. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 datalength tag channel tcode sy asynchronous stream data spd errcode table 4-2-2 asynchronous stream receive format
MD8412B 44 fujifuilm microdevices co., ltd. ver 1.10 4-3 isochronous 4-3-1 normal mode 4-3-1-1 transmit datalength : data length field the data length of blockdata field is stored in this field. tag : tag field the tag of isochronous transfer is stored in this field. channel : channel field the isochronous transfer channel number is stored in this field. spd : speed field a transmitting speed is defined in this field. as for the setting value, refer to table 4-6-6. sy : sync field the sync of isochronous transfer is stored in this field. isochronous data : isochronous data field this field is used to set up actual transfer data. if the datalength field is not defined with a multiple of 4, this field is required to be completed so that the quadlet unit is finished with 00h. 313029282726252423222120191817161514131211109876543210 datalength tag channel tcodec spd sy isochronous data padding (if necessary) table 4-3-1 block transmit format (isochronous: normal)
MD8412B ver 1.10 fujifuilm microdevices co., ltd. 45 4-3-1-2 receive datalength :data length field the data length of the transferred blockdata field is stored in this field. tag : tag field the tag of isochronous transfer is stored in this field. channel : channel field the isochronous transfer channel number is stored in this field. sy : sync field the sync of isochronous transfer is stored in this field. tcode : tcode field the tcode of isochronous transfer is stored in this field. the value "ah" is stored. isochronous data : isochronous data field the actual transfer data is stored in this field. spd : speed field the speed of reception is stored in this field. for values, refer to table 4-6-6. errcode : error code field an acknowledge signal at the time of reception is stored in this field. unlike the case of asynchronous data transfer, however, no value of this field is returned. for more details, refer to table 4-6-7. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 datalength tag channel tcode sy isochronous data spd errcode table 4-3-2 block receive format (isochronous: normal)
MD8412B 46 fujifuilm microdevices co., ltd. ver 1.10 4-3-2 auto-mode 4-3-2-1 transmit isochronous data : isochronous data field this field is used to set up actual transfer data. if the datalength field is not defined with a multiple of 4, this field need be filled with 00h to complete it in the quadlet unit. 4-3-2-2 receive isochronous data : isochronous data field the transferred data are saved in this field. 313029282726252423222120191817161514131211109876543210 isochronous data table 4-3-3 block transmit format (isochronous: auto) 313029282726252423222120191817161514131211109876543210 isochronous data table 4-3-4 block receive format (isochronous: auto)
MD8412B ver 1.10 fujifuilm microdevices co., ltd. 47 4-4 snoop snoopeddata : snooped data field third field is used to save the snooped data. spd : speed field this field is used to save the received speed. refer to table 4-6-6 regarding setting values. snpstat : snooped status field this field saves the ack code to be returned as a status (acknowledge) signal after this packet has been received. actually, however, the ack code is not returned. refer to table 4-6-7 regarding details. acksnp : snooped ack-code field this field saves the received ack code. in other words, a node that has received this packet corresponds to the returned ack code. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 snooped data spd snpstat acksnp table 4-4-1 snoop receive format
MD8412B 48 fujifuilm microdevices co., ltd. ver 1.10 4-5 selfid packet after the identification quadlet data shown in table 4-4-1 have been saved, an actual selfid packet is saved. this operation is completed with the last quadlet id data as shown in table 4-4-4. phy_id : physical_id field a node id of the phy chip used to send this packet. l : link_active field 0 = link is not active. 1 = active link and transaction layer are present in this node. gap_cnt : gap_count field a present value of the phy_configuration.gap_count field for this node is saved. 313029282726252423222120191817161514131211109876543210 000000000000000000000000 1110b 0000 table 4-5-1 selfid packet receive format (first quadlet) 313029282726252423222120191817161514131211109876543210 1 0 phy_id 0 l gap_cnt sp del c pwr p0 p1 p2 i m logical inverse of first quadlet table 4-5-2 selfid packet receive format (selfid packet #0) 313029282726252423222120191817161514131211109876543210 1 0 phy_id 1 n rsv pa pb pc pd pe pf pg ph r m logical inverse of first quadlet table 4-5-3 selfid packet receive format (selfid packet #1, #2, & #3) 313029282726252423222120191817161514131211109876543210 0000000000000000000000000000 acksent table 4-5-4 selfid packet receive format (last quadlet) n papbpcpdpe pf pgph pkt #10 p3p4p5p6p7p8p9p10 pkt #2 1 p11 p12 p13 p14 p15 p16 p17 p18 pkt #3 2 p19 p20 p21 p22 p23 p24 p25 p26 table 4-5-5 selfid packet receive format (pn)
MD8412B ver 1.10 fujifuilm microdevices co., ltd. 49 sp : phy_speed field 00 = 98.304mbps 01 = 98.304 and 196.608mbps 10 = 98.304 and 196.608 and 393.216mbps 11 = reserved available speeds are saved. del : phy_delay field 00 = 144ns or less (~14/base_rate) 01~11= reserved. the delay time of the repeater in the worst case is saved. c : contender field when this field is set and the link_active field is also set, this node indicates that it can be a bus or isochro- nous resource manager. pwr : power_class field 000 = the node does not require power supply. 001 = the node does has its own power supply that can feed a minimum of 15w. 010 = the node does has its own power supply that can feed a minimum of 30w. 011 = the node does has its own power supply that can feed a minimum of 45w. 100 = the node consumes a maximum of 1w of power from the cable. in addition, it consumes a maximum of 2w to enable the link and upper layers. 101 = the node consumes a maximum of 1w of power from the cable. in addition, it consumes a maximum of 2w to enable the link and upper layers. 110 = the node consumes a maximum of 1w of power from the cable. in addition, it consumes a maximum of 5w to enable the link and upper layers. 111 = the node consumes a maximum of 1w of power from the cable. in addition, it consumes a maximum of 9w to enable the link and upper layers. p0... p26 : nort,child[nport],connected[nport]field 11 = connected to the parent node. 10 = connected to the parent node. 01 = not connected to another phy. 00 = this phy is not offered. the port status is shown. i : initiated_reset field if it is set, this node has issued present bus reset. m : more_packets field if it is set, this node indicates that another selfid packet of this node is closely following. n : extended field an extension selfid packet sequence number (value from 0~2). r, rsv : reserved field reserved.
MD8412B 50 fujifuilm microdevices co., ltd. ver 1.10 4-6 phy control packet 4-6-1 phy control packet transmit to send a phy control packet, the first quadlet of data shown in table 4-5-4 is saved in the atf buffer, and the phy con- trol packet specified by 1394 is then saved. in this case, it is necessary to save the phy control packet data together with th e reversal data. in actual transmission, the first quadlet is not sent and the phy control packet only is sent. refer to the draft regarding details. 4-6-2 phy control packet receive when phy control packet is received, the data which shows it to original quadlet in the table 4-6-1 is stored in the arf buffer. the phy control packet established with 1394 after that is stored. at this time, the invert data of phy control packet isn?t stored in the arf buffer. and, when the phy received pingpacket has more than 4port, that selfid packet isn?t stored in the arf buffer. and, that phy control packet isn?t stored in the arf buffer when the invert data of the phy control packet is different. refer to the draft regarding details. 4-7 code the codes used for packet formatting specified by 1394 are shown. refer to the 1394 draft for details of each code. 313029282726252423222120191817161514131211109876543210 1110b table 4-6-1 phy control packet format (first quadlet) code name 00b retry_1 01b retry_x 10b retry_a 11b retry_b table 4-7-1 list of retry code
MD8412B ver 1.10 fujifuilm microdevices co., ltd. 51 code name code name 0h write request for data quadlet 8h cycle start 1h write request for data block 9h lock request 2h write response ah isochronous data block 3h reserved bh lock response 4h read request for data quadlet ch isochronous data block (copyright) 5h read request for data block dh reserved 6h read response for data quadlet eh reserved 7h read response for data block fh reserved table 4-7-2 list of transaction code (tcode) destination bus_id destination node_id contents 0 ~ 3feh 0 ~ 3eh transferred to the node defined by bus_id and node_id. 3ffh 0 ~ 3eh transferred to the node defined by node_id in local bus. 0 ~ 3feh 3fh broadcast transfer to the bus defined by bus_id. 3ffh 3fh broadcast transfer in local bus. table 4-7-3 list of bus number / node number data rate maximum payload size (byte) 100mbps 512 200mbps 1024 400mbps 2048 table 4-7-4 list of data length (data length)
MD8412B 52 fujifuilm microdevices co., ltd. ver 1.10 code name 0000h reserved 0001h mask_swap 0002h compare_swap 0003h fetch_add 0004h little_add 0005h bounded_add 0006h wrap_add 0007h vender_dependent 0008h ~ ffffh reserved table 4-7-5 list of extension transaction code (extend tcode) code speed 00b 100mbps 01b 200mbps 10b 400mbps 11b reserved table 4-7-6 list of speed codes (spd)
MD8412B ver 1.10 fujifuilm microdevices co., ltd. 53 code name 0h reserved 1h ack_complete 2h ack_pending 3h reserved 4h ack_busy_x 5h ack_busy_a 6h ack_busy_b 7h reserved 8h reserved 9h reserved ah reserved bh reserved ch reserved dh ack_data_error eh ack_type_error fh reserved table 4-7-7 list of acknowledge codes (ack)
MD8412B 54 fujifuilm microdevices co., ltd. ver 1.10 5 functional description 5-1 host interface control of MD8412B and transmission/reception data transfer are all conducted through host interface. timing for host interface signals is controlled by the respective signals of cs#, rd#, wr#, ha(6:0), and hd(31:0) for asynchronous transfer as sram interface. the internal register and the p1394 packet format are basically in the bus width of 32 bits. the MD8412B can, however, control the bus width so that it can be connected to an mpu that has an 8-bit, 16-bit, or 32-bit data bus. 5-1-1 register access timing as shown in figure 5-1-1, access to a register is effected through the sram-like asynchronous bus. figure 5-1-1 host access timing 5-1-2 host bus width as shown in table 5-1-1, a valid bit accessed from the host is determined by uwe#, ube#, ha1, and ha0. therefore, if controlling the MD8412B with an 8-bit mpu, the bit is fixed at uwe="1" and ube="1" and the address and data bus are connected to ha(6:0) and hd(7:0). in this manner, direct control is possible. for reading/writing in the byte unit with an 8-bit mpu, it is always necessary to do it in the unit of 4 bytes. for a 16-bit mpu, this must be done in the unit of 2 words. the register access normally operates when an ordinary address is specified uwe# ube# ha1 ha0 access valid host bus buffer bit position 0000 quadlet 31 - 0 31 - 0 1000word15 - 031 - 16 1010word15 - 0 15 - 0 1100byte7 - 0 31 - 24 1101byte7 - 0 23 - 16 1110byte7 - 0 15 - 8 1111byte7 - 0 7 - 0 table 5-1-1 valid host data bus accessed from the host ha cs# wr# rd# hd write register read register
MD8412B ver 1.10 fujifuilm microdevices co., ltd. 55 and writing/reading is effected there. when performing writing/reading with transmission/reception buffer in the MD8412B, data are stored in turn in the buffer, starting with an upper area as shown in table 5-1-2. the same thing can be said for dma transfer. the first one byte is written/read-out from the upper area. if the little-endian bit is set at with a 16 - or 32-bit width, bytes are rearranged for buffer writing/reading, as shown in table 5-1-2. table 5-1-2 little / big endian mode 31 0 31 0 15 0 15 0 31 0 31 0 15 15 00 15 0 15 0 70 7 0 7 07 0 n n+1 n+2 n+3 n+3 n+2 n+1 n n n+1 n+2 n+3 n n+1 n+2 n+3 n n+1 n+2 n+3 n+1 n n+3 n+2 nn+1n+2n+3 n n+1 n+2 n+3 n n+1 n+2 n+3 15 0 15 0 mpu register link buffer mpu register link buffer mpu register and link buffer quadlet word byte big-endian littele-endian 4n 4n 2n 2n+1 2n 2n+1
MD8412B 56 fujifuilm microdevices co., ltd. ver 1.10 5-1-3 dma transfer the MD8412B supports the dma transfer functions to assure the method of data transfer with the transmission/reception buffer. the dma mode is supported only that the dma service request signal (dreq) is of a level sense. only one objec- tive buffer for dma transfer can be selected with the selectdreq bit. whether the dreq signal should be made valid or not is controlled by the dreqen bit. for dreqen="1", the dreq signal is valid, table 5-1-3 shows the assert/negate condi- tions of the dreq signal. for dreqen="0" the dreq signal always stays in the negate state. when transferring the transmission data, necessary data size is defined at the external dmac and then data transfer is effected. since then, dma transfer is effected by setting dreqen at "1" and issuing a dreq request toward the dmac. when transferring the reception data to the host side, the data length is read first and its value is set at the dmac then execute the dmac. since then, dma transfer is effected by setting dreqen at "1" and issuing a dreq request toward the dmac. figure 5-1-2 dma transfer timing described below is an additional explanation about the negate timing for the dma service request signal (req). as shown in table 5-1-3, the negate conditions are created when the internal buffer is for full-1 quadlet. when full writ- ing is conducted by entering the wr# input, the dreq signal is negated as shown in fig. 5-1-2. selectdreq bit destination buffer dreq assert condition dreq negate condition 00b atf when atf buffer is not full. when atf buffer is full. (atffull="1") 01b arf when data remain in arf buffer. when arf buffer is full. (arfempty="1") 10b itf/irf when itf buffer is not full. when itf buffer is full. (itffull="1") 11b irf when data remain in irf buffer. when irf buffer is full. (irfempty="1") table 5-1-3 dreq signal assert / negate conditions dreq dack# rd# hd wr#
MD8412B ver 1.10 fujifuilm microdevices co., ltd. 57 figure 5-1-3 dreq negate timing (wr#) figure 5-1-4 dreq negate timing (rd#) 5-1-4 interrupt processing as a means of announcement to the host regarding the interrupt factor defined by the interrupt register and the interrupt mask register, the MD8412B is provided with an int# signal. this int# signal is asserted under the condition that logical or is established for the interrupt factor not masked at the interrupt mask register with active low. regarding the negate condition, all bits are cleared to "1" by reading them out from the interrupt register. t sckc max 4* t sckc+20ns sysclk wr# dreq min 3* t sckc t sckc max 2* t sckc+20ns sysclk wr# dreq min t sckc
MD8412B 58 fujifuilm microdevices co., ltd. ver 1.10 5-2 phy-chip interface interface with the phy-chip is established with the sysclk, lreq,d(7:0), ctl(1:0) signals. for connection with the phy-chips that have various maximum speeds, the d(7:0) signal is used to select 100mbps, 200mbps, and 400mbps. con- nection with a 100mbps phy chip is made by d(1:0), that with a 200mbps phy-chip is made by d(3:0), and that with a 400mbps phy-chip is made by d(7:0) to enable communication. 5-2-1 connecting method regarding the method of connection with phy-chips, the MD8412B is designed to support dc connections only. there- fore, the method of connection is as shown in figure 5-2-1. connection with the MD8412B, a 200mbps phy-chip, is possible by making a connection between the lower 4 bits of the d(7:0) terminal and the md8401. (see figure 5-2-2) figure 5-2-1 connection between MD8412B and phy-chip sysclk lreq d(7:0) ctl(1:0) link_on pps vdd link chip MD8412B phy chip direct
MD8412B ver 1.10 fujifuilm microdevices co., ltd. 59 figure 5-2-2 connection between MD8412B and md8404 5-2-2 phy-chip control to control the phy-chip, the MD8412B employs communication means defined by the following 4 types of operation modes. each operation mode is defined according to the condition of ctl(1:0) terminal. after control of the phy-link bus has been enabled in the above transmit mode, the operation mode shown in table 5- 2-2 is valid. ctl[0:1] operation contents 00b idle idle condition and nothing is operating (default mode) 01b status status information transferred from phy-chip 10b receive contents of received packet transferred from phy-chip 11b transmit phy-link bus controlled for MD8412B to transfer a transmission packet to phy-chip table 5-2-1 phy-chip control mode 1 ctl[0:1] operation contents 00b idle phy-link bus released upon completion of transfer by MD8412B 01b hold - bus held for MD8412B transfer until definition of data - MD8412B requesting for another packet sending without arbitration 10b transmit data of a transmission packet transferred to phy-chip 11b reserved reserved table 5-2-2 phy-chip control mode 2 sysclk lreq d(7:0) ctl(1:0) lps link chip MD8412B phy chip sysclk lreq d(3:0) ctl(1:0) lps md8404 ac coupling circuite direct direct
MD8412B 60 fujifuilm microdevices co., ltd. ver 1.10 5-2-3 request as a request to access a register of the phy-chip or a phy-link bus, MD8412B sends a short serial stream to the lrec terminal. the stream involves information about the type requested, speed of the packet transferred, and the reading/writ- ing command. figure 5-2-3 lreq stream 5-2-3-1 lreq a request for phy-link bus is placed in lreq by a format with the length of 7 bits as shown in table 5-2-3. a request for phy-chip register read-out is placed in lreq by a format with the length of 9 bits as shown in table 5-2- 5. a request for phy-chip register writing is placed in lreq by a format with the length of 17 bits as shown in table 5-2- 6. bit(s) type contents 0 start bit showing the start of transfer. "1"is always transferred. 1~3 request type indicating a requested type as specified in table 5-2-6. 4~5 request speed indicating the transfer speed of the requesting phy-chip. 6 stop bit showing the end of transfer. "0" is always transferred. table 5-2-3 request format lreq[4:5] data rate 00 100mbps 01 200mbps 10 400mbps 11 >400mbps table 5-2-4 speed format lr0 lr1 lr2 lr3 lr4 lr n-1 lr n lrn = lreqn
MD8412B ver 1.10 fujifuilm microdevices co., ltd. 61 bit(s) type contents 0 start bit showing the start of transfer. "1"is always transferred. 1~3 request type indicating a requested type as specified in table 5-2-6. 4~7 address indicating register address of the read-out phy-chip. 8 stop bit showing the end of transfer. "0" is always transferred. table 5-2-5 read register format bit(s) type contents 0 start bit showing the start of transfer. "1"is always transferred. 1~3 request type indicating a requested type as specified in table 5-2-6. 4~7 address indicating register address of the writing-in phy-chip. 8~15 data indicating register address of the writing-in phy-chip. 16 stop bit showing the end of transfer. "0" is always transferred. table 5-2-6 write register format bit(s) type contents 0 start bit showing the start of transfer. "1"is always transferred. 1~3 request type indicating a requested type as specified in table 5-2-6. 4 accelerate this indicates that the arbitration acceleration is disabled for accelerate "0" and enabled for accelerate "1". 5 stop bit showing the end of transfer. "0" is always transferred. table 5-2-7 acceleration control format lreq[1:3] type contents 000 immreq immediate request 001 isoreq isochronous request 010 prireq priority request 011 fairreq fair request 100 rdreg reading out the contents of the set register 101 wrreg writing in the set register 110, 111 reserved reserved table 5-2-8 request type
MD8412B 62 fujifuilm microdevices co., ltd. ver 1.10 5-2-4 transfer 5-2-4-1 status request figure 5-2-4 status request bit(sn) type contents 0 arbitration reset gap detection of arbitration reset gap 1 fair gap detection of fair gap 2 bus reset detection of bus reset 3 phy interrupt requesting the host for interrupt 4~7 address address of the status-returning phy register 8~15 data status data table 5-2-9 status request format ctl[0:1] 00 01 01 01 01 01 00 00 d[0:1] 00 s[0:1] s[2:3] s[4:5] s[6:7] s[14:15] 00 00
MD8412B ver 1.10 fujifuilm microdevices co., ltd. 63 5-2-4-2 singlepackettransmit figure 5-2-5 singlepackettransmit ctl[0:1] 00 11 00 zz zz zz zz zz zz zz zz 00 phy drive d[0:1] 00 00 00 zz zz zz zz zz zz zz zz 00 ctl[0:1] zz zz zz 01 01 10 10 10 10 00 00 zz MD8412B drive d0 z z z 0 0 d0 d2 d4 d 2n 0 0 z 100mbps d1 z z z 0 0 d1 d3 d5 d 2n+1 0 0 z d0 z z z 0 0 d0 d4 d8 d 4n 0 0 z 200mbps d1 z z z 0 0 d1 d5 d9 d 4n+1 0 0 z d2 z z z 0 0 d2 d6 d10 d 4n+2 0 0 z d3 z z z 0 0 d3 d7 d11 d 4n+3 0 0 z
MD8412B 64 fujifuilm microdevices co., ltd. ver 1.10 5-2-4-3 concatenated packet transmit figure 5-2-6 concatenated packet transmit ctl[0:1] zz zz zz 00 00 11 00 zz zz zz zz zz phy drive d[0:1] zz zz zz 00 00 00 00 zz zz zz zz zz ctl[0:1] 10 01 00 zz zz zz zz 01 01 10 10 10 MD8412B drive d0 d 2n-1 sp 0 z z z z 0 0 d1 d3 d5 100mbps d1 d 2n sp 0 z z z z 0 0 d2 d4 d6 d0 d 2n-3 sp 0 0 z z z 0 0 d0 d4 d8 200mbps d1 d 2n-2 sp 0 0 z z z 0 0 d1 d5 d9 d2 d 2n-1 sp 0 0 z z z 0 0 d2 d6 d10 d3 d 2n sp 0 0 z z z 0 0 d3 d7 d11
MD8412B ver 1.10 fujifuilm microdevices co., ltd. 65 5-2-4-4 receive figure 5-2-7 receive sp[0:7] data rate 00xxxxxx 100mbps 0100xxxx 200mbps 01010000 400mbps figure 5-2-8 speed code (sp[0:7]) ctl[0:1] 00 10 10 10 10 10 10 10 10 00 00 00 phy drive d0 0 1 1 1 1 sp0 d0 d2 d 2n 0 0 0 100mbps d1 0 1 1 1 1 sp1 d1 d3 d 2n+1 0 0 0 d0 0 1 1 1 1 sp0 d0 d4 d 4n 0 0 0 200mbps d1 0 1 1 1 1 sp1 d1 d5 d 4n+1 0 0 0 d2 0 1 1 1 1 sp2 d2 d6 d 4n+2 0 0 0 d3 0 1 1 1 1 sp3 d3 d7 d 4n+3 0 0 0
MD8412B 66 fujifuilm microdevices co., ltd. ver 1.10 5-2-5 phy-link i/f reset timing the disable/enable control of the phy-link interface is carried out with the MD8412B terminal and lps. the output control of the lps signals is performed as described below, by the use of the lpson bit in the register of this device, together with the external terminals and the direct terminal. figure 5-2-9 lps output waveform in ac connection this device is provided with the two systems of phy-link interface reset timing. the changeover operation for the reset timing is effected with the phyifrst bit in the register. the phyifrst bit is set at "0" if the phy chip connected to this device is for the device other than the one conforming to 1394a. in this case, the lps terminal generates an output at the low level shortly after the lpson bit has been set at "l" in the register. then, the phy-link interface reset sequence is started. in 1.2s after the fall of the lps signal, this device gen- erates an output of ctl (1:0) and d (7:0) at the high-z level if an ac connection has been made or at the low level in the case of a dc connection. when the lpson bit is set at "1" again, the lps terminal begins to generate a clock output if an ac connection has been made or an output at the high level in the case of a dc connection. after the rise of the lps signal at that time, an output of ctl (1:0) is generated at the "l" level with the timing of the front sclk in order to complete the phy-link interface reset sequence. direct lpson lps output 10 0 11 1 00 0 01 approx. 0.6 to 3.6mhz clock (duty 33%) table 5-2-10 lps output symbol explanation min max unit t lpsh lps"h" period in ac connection 0.09 0.50 s t lpsl lps"l" period in ac connection 0.19 1.00 s table 5-2-11 lps output characteristics in ac connection t lpsh t lpsl
MD8412B ver 1.10 fujifuilm microdevices co., ltd. 67 figure 5-2-10 phyifrst="0"; phy-link i/f reset sequence in ac connection the phyifrst bit is set at "1" if the phy chip connected to this device is for the device other than the one conforming to 1394a. also in this case, the lps terminal generates an output at the low level shortly after the lpson bit has been set at "l" in the register. then, the phy-link interface reset sequence is started. in 1.2s after the fall of the lps signal, this device generates an output of ctl (1:0) and d (7:0) at the high-z level if an ac connection has been made or at the low level in the case of a dc connection. when the lpson bit is set at "1" again, the lps terminal begins to generate a clock output if an ac connection has been made or an output at the high level in the case of a dc connection. after the rise of the lps signal at that time, an output of ctl (1:0) and d (7:0) is generated at the "l" level for the dura- tion of 1sclk within 6 cycles after the first sclk. in the case of a dc connection, an output is generated at the "l" level. since then, dataprefix idle is received from the phy chip in order to complete the phy-link interface reset sequence. figure 5-2-11 phyifrst="1"; phy-link i/f reset sequence in ac connection within lps sclk ctl(0:1) 1.2s within lps sclk ctl(0:1) d(7:0) 1.2s
MD8412B 68 fujifuilm microdevices co., ltd. ver 1.10 5-3 buffer access 5-3-1 buffer configuration the MD8412B incorporates a memory buffer with a total capacity of 2k-bytes in 512x32word configuration. to achieve rate absorption in terms of host access rate and serial bus transfer rate, the buffer is temporarily used between host bus and transmitter. the buffer control block of MD8412B divides this buffer into a maximum of 4 blocks, and control is effected in the unit of divided sub-buffer. two blocks are assigned to asynchronous transmission and reception. (referred to as atf for asynchronous transmission buffer and arf for asynchronous reception buffer) when performing isochronous transmission or reception, the relevant buffers are assigned to the remaining two blocks. according to the contents of isomode setting register in the control register, however, combination of these two blocks is defined if they are to be used for transmit/receive, or receive/receive, or receive only. in the isochronous mode other than isomode="011" or "101" two sub-buffers are assigned for isochronous transmission and reception, respectively. when iso- mode="011" two isochronous channels are limited to reception only, and hence isochronous transmission is impossible to achieve. when isomode ="101" only one sub-buffer for receive. for these reasons, one of the two sub-buffers is changed over for isochronous reception when isochronous transfer is attempted, and the other is changed over for transmission and reception through isomode setting. (referred to as atf/irf for asynchronous transmission/isochronous reception buffer and irf for isochronous reception buffer hereafter) from the host, access is made to atf from the atf register, arf from the arf register, irf from the irf register, and itf/irf from the itf/irf register. figure 5-3-1 buffer assignment in cases other than isomode="011b" atf register arf register itf/irf register irf register asynchronous transmitter buffer(atf) asynchronous receiver buffer(arf) isochronous transmitter buffer(itf) isochronous receiver buffer(irf) register memory buffer 512*32word=2kbyte host transmitter receiver
MD8412B ver 1.10 fujifuilm microdevices co., ltd. 69 figure 5-3-2 buffer assignment in the case of isomode="011b" 5-3-2 size setting for each sub-buffer before actual transmission/reception, it is first of all necessary to set up a sub-buffer size. setting for asynchronous oper- ation is made with an asynchronous buffer size set register and that for isochronous operation is made with an isochro- nous buffer size set register. asynchronous buffer size setting is made based on asynchronous transmission/reception total size (total size = atf size + arf size) and reception buffer size (arf size). from these settings, the transmission buffer size is atf size = total size - arf size. the setting unit is quadlet. the setting size must be at least more than the quadlet figure of the transmitting packet for transmission, and more than the quadlet figure of the receiving packet for reception. if the atf size is set smaller than the transmitting packet size, the MD8412B cannot transmit this packet. if arf is set smaller than the receiving packet size, the MD8412B returns busy acknowledge to the sending node and the packet buffering cannot be made completely within the arf. setting for isochronous buffer size is similar to that for asynchronous. for isomode setting other than "011" and "101" itf and irf settings are made with isochronous total buffer and irf size. when isomode="011" size setting is to be made for two irf buffers. in this case also, total buffer size and irf size are set. in this case, the total size (itotalsize) is a total of two receiving buffer sizes. irf size (irxbuffersize) is size of irf buffer while an isochronous packet set by isochronous configuration register-3 is received. buffer size of the remaining one channel is total size - irf size. the sub-buffer for that size is itf/irf for an isochronous packet of isochronous con- figuration register-2. for isomod="101" the isochronous buffer is not divided, and one receiving sub-buffer is set up. this buffer is irf. for the size setting, contents of the total buffer size (itotalsize) must be identical with those of irxbuffersize. atf register arf register itf/irf register irf register asynchronous transmitter buffer(atf) asynchronous receiver buffer(arf) isochronous receiver buffer 1(irf1) isochronous receiver buffer 2(irf2) register memory buffer 512*32word=2kbyte host transmitter receiver
MD8412B 70 fujifuilm microdevices co., ltd. ver 1.10 figure 5-3-3 sub-buffer size assignment 5-3-3 buffer access by bus width as a method of access to a buffer, the MD8412B is provided with means of soft access and dma access. each method is described below. 5-3-3-1 soft access since ieee p1394 offers packet configuration of the quadlet unit, method can differ according to the width of bus to be accessed. for a 32-bit width, data of one quadlet can be written/read with a register corresponding to the directly control- ling buffer. for an 8/16-bit width, however, data of one quadlet must be divided and written/read 4 times for 8 bits, or twice for 16 bits. at first, procedures of writing in the atf buffer in 8-bit width are described below. data for 1 byte are written in a 40h register. writing is then forwarded in the order of 41h, 42h, and 43h. when writing for 43h is finished, data for one quadlet become valid. therefore, writing must be forwarded always in the order of 40h, 41h, 42h, and 43h. 31 atf register 0 7 - - - - - - - - - - 0 7 - - - - - - - - - - 0 7 - - - - - - - - - - 0 7 - - - - - - - - - - 0 40h 41h 42h 43h figure 5-3-4 register operation (atf) for 8-bit width soft access arf atf arecbuffersize atotalsize - arecbuffersize atotalsize asynchronous buffer size set register irf itf/irf irecbuffersize itotalsize - irecbuffersize itotalsize isochronous buffer size set register atotalsize + itotalsize < 2kbyte
MD8412B ver 1.10 fujifuilm microdevices co., ltd. 71 similarly, when reading out data from an arf buffer, the reading order of 44h, 45h, 46h, and 47h must be followed. sit- uation is the same as for the isochronous itf/irf and irf buffers. when writing data in an atf buffer in 16-bit width, writing for 8-bit width must be repeated 4 times. in this case, similar process must be followed for accessing, repeating writing twice. at first, data for 1 word are written in a 40h register. writing is then forwarded in the order of 42h. when writing for 42h is finished, data for one quadlet become valid. therefore, writing must be forwarded always in the order of 40h and 42h. similarly, when reading out data from an arf buffer, it is necessary to read in the order of 44h and 46h. situation is the same as for the isochronous itf/irf and irf buffers. 5-3-3-2 dma access it is necessary to designate an objective buffer for dma access using a selectdreq bit. at first, procedures for writing in an atf buffer in 8-bit width are described below. in the first place, selectdreq=00b is set to make atf an object of dma transfer and dmawidth=00b to designate 8-bit width transfer. when dmac is started and dreqen is then turned "1" a dreq request is issued toward the dmac and dma transfer is started. in this case, the first 1 byte is stored in 32~24 bit of the atf buffer and the second byte is stored in 23~16 bit. likewise, the third byte is stored in 15~8 bit and the 4th byte is stored in 7~0 bit. finally, data become valid as 1-quadlet data. accordingly, the number of dma transfers must be always a multiple of 4. 31 arf register 0 7 - - - - - - - - - - 0 7 - - - - - - - - - - 0 7 - - - - - - - - - - 0 7 - - - - - - - - - - 0 44h 45h 46h 47h figure 5-3-5 register operation (arf) for 8-bit width soft access 31 atf register 0 15 - - - - - - - - - - - - - - - - - - - - - 0 15 - - - - - - - - - - - - - - - - - - - - - 0 40h 42h figure 5-3-6 register operation (atf) for 16-bit width soft access 31 arf register 0 15 - - - - - - - - - - - - - - - - - - - - - 0 15 - - - - - - - - - - - - - - - - - - - - - 0 44h 46h figure 5-3-7 register operation (arf) for 16-bit width soft access
MD8412B 72 fujifuilm microdevices co., ltd. ver 1.10 similarly, operation is the same when data are read from the arf buffer by dma transfer. data are read from the upper area of 32 bit. operation is the same as for 16-bit width. selectdreq=00b is set to make atf an object of dma transfer, and dmaw- idth=01b is set to designate16-bit width transfer. when dmac is started and dreqen is turned "1" thereafter, a dreq request is issued toward the dmac, and dma transfer is started. in this case, the first 1 word is stored in 31~16 bit of the 31 atf register 0 7 - - - - - - - - - - 0 7 - - - - - - - - - - 0 7 - - - - - - - - - - 0 7 - - - - - - - - - - 0 1?st byte 31 atf register 0 7 - - - - - - - - - - 0 7 - - - - - - - - - - 0 7 - - - - - - - - - - 0 7 - - - - - - - - - - 0 2?nd byte 31 atf register 0 7 - - - - - - - - - - 0 7 - - - - - - - - - - 0 7 - - - - - - - - - - 0 7 - - - - - - - - - - 0 3?rd byte 31 atf register 0 7 - - - - - - - - - - 0 7 - - - - - - - - - - 0 7 - - - - - - - - - - 0 7 - - - - - - - - - - 0 4?th byte figure 5-3-8 register operation (atf) for 8-bit width dma access 31 arf register 0 7 - - - - - - - - - - 0 7 - - - - - - - - - - 0 7 - - - - - - - - - - 0 7 - - - - - - - - - - 0 1?st byte 31 arf register 0 7 - - - - - - - - - - 0 7 - - - - - - - - - - 0 7 - - - - - - - - - - 0 7 - - - - - - - - - - 0 2?nd byte 31 arf register 0 7 - - - - - - - - - - 0 7 - - - - - - - - - - 0 7 - - - - - - - - - - 0 7 - - - - - - - - - - 0 3?rd byte 31 arf register 0 7 - - - - - - - - - - 0 7 - - - - - - - - - - 0 7 - - - - - - - - - - 0 7 - - - - - - - - - - 0 4?th byte figure 5-3-9 register operation (arf) for 8-bit width dma access
MD8412B ver 1.10 fujifuilm microdevices co., ltd. 73 atf buffer and the second word is stored in 15~0 bit. finally, data become valid as 1-quadlet data. accordingly, the num- ber of dma transfers must be always a multiple of 2. similarly, operation is the same when data are read from the arf buffer by dma transfer. data are read from the upper area of 32 bits. 5-3-4 buffer control asynchronous buffer control is different from isochronous buffer control. each control is described below. 5-3-4-1 asynchronous buffer control for both asynchronous transmission and reception, the host gains access to a buffer in the packet unit. accordingly, as described previously, the size must always be larger than one packet when specifying a packet size for transmission and reception. otherwise, the MD8412B cannot send out that packet in transmission phase. in reception phase, a busyack code is returned. 31 atf register 0 15 - - - - - - - - - - - - - - - - - - - - - 0 15 - - - - - - - - - - - - - - - - - - - - - 0 1?st word 31 atf register 0 15 - - - - - - - - - - - - - - - - - - - - - 0 15 - - - - - - - - - - - - - - - - - - - - - 0 2?nd word figure 5-3-10 register operation (atf) for 16-bit width dma access 31 arf register 0 15 - - - - - - - - - - - - - - - - - - - - - 0 15 - - - - - - - - - - - - - - - - - - - - - 0 1?st word 31 arf register 0 15 - - - - - - - - - - - - - - - - - - - - - 0 15 - - - - - - - - - - - - - - - - - - - - - 0 2?nd word figure 5-3-11 register operation (arf) for 16-bit width dma access
MD8412B 74 fujifuilm microdevices co., ltd. ver 1.10 5-3-4-1-1 transmission buffer when data are sent from the host to a buffer in transmission phase and atgo is issued, the data contained in the aft are regarded as 1 packet. if there is still an empty in the atf buffer after the issuing of atgo, the host can write data of the next sending packet in this atf. in this manner, the MD8412B performs reciprocal control of atf in one-packet unit on host side and transmitter side. if the buffer status is not of empty, the quantity of data the host can write next may be arbi- trarily controlled according to the atf size set by the buffersizeset register and the packet size presently being handled for transmission by atgo. therefore, even though the bufferstatus register is not supervised, the host can identify vacancy in buffers at any time. the packet data presently transmitted are kept buffered in the atf until ack code of complete or pending is returned from the related destination node. when the ack code is busy, the data buffered in the middle of retry phase are repeatedly trans- mitted according to the frequency of retry. when a retry count value is exceeded the max value, or complete or pending ack code is returned during the operation, the area in the atf, where the packet is contained, is automatically flushed. if an erro r ack code is received in the retry phase, this phase is stopped at that time point and flushing is effected regardless of whethe r the retry maximum value is attained. in this case, even if the host has already written the next sending packet in a vacant are a of atf in the buffer, there is no influence on the data. when atf reset is effected with resetatf bit in the reset register, the atf is restored to its initial condition and all data contained therein are lost, thus making the empty flag active. figure 5-3-12 concept of atf operation packet1 atgo packet2 packet3 packet1 packet1 packet2 packet2 packet2 packet2 packet3 packet2 packet2 packet3 command atgo command atgo command (a) (c) (e) (b) (d) (f) (g) host(write) atf link(tranceiver)
MD8412B ver 1.10 fujifuilm microdevices co., ltd. 75 5-3-4-1-2 reception buffer handling of the arf for asynchronous reception buffer is basically the same as for transmission. when all contents of the received packet have been written in the arf by the receiver, the host can read out the packet from the arf. at that time, even though the host does not read out the packet from the arf, writing operation into the arf of the next packet from the receiver is effected, provided that there is still another vacancy in the arf buffer. in this fashion, reciprocal con- trol is effected even in the arf. for example, assuming that the arf presently contains one packet that can already be read out by the host and the next packet written from the receiver, the timing to permit writing of a new packet from the receiver into the arf is defined as when the host has read out all contents of one packet. therefore, under the condition that data of one packet plus a are remaining in the arf, the receiver cannot write a new packet in the arf. as a result, a busyack code is returned to the source node and a request is made for another transmission of the packet. when the host reads out a received packet from the MD8412B and concludes according to the contents that the header and successive data are not required for a certain reason, the host can flush all the data from the arf using the arfflush bit in the buffercon- trol register, without performing wasteful reading of these data. even when writing of a packet by the receiver has been already finished into the arf, there is no influence on these data. when arf reset is effected with resetarf bit in the reset register, the arf is restored to its initial condition and all data contained therein are lost. if the full bit has been active, it is turned non-active. figure 5-3-13 concept of arf operation packet2 packet2 packet2 packet2 packet3 (f) (g) (h) packet3 packet3 packet5 packet5 packet1 packet2 packet4 packet1 packet1 packet2 packet2 (a) (c) (e) (b) (d) link(receiver) arf host(read) packet3 packet3
MD8412B 76 fujifuilm microdevices co., ltd. ver 1.10 5-3-4-2 isochronous buffer control 5-3-4-2-1 normal mode buffer control for isochronous transmission in normal mode is basically the same as for asynchronous buffer control. control of transmission buffers is also reciprocally performed. difference from asynchronous operation is that it is not a reciprocal changeover of a packet unit between host side and transmitter side, but it is done in the unit of packet group for several different channels to be transmitted in a certain isochronous cycle. the number of packets that can be stored in the buffer during transmission is for the maximum number of channels inso- far as the buffer has a vacant area. packets for several channels that must be transmitted by the host in some cycle period are written in the itf/irf buffer and itgo is then issued. the MD8412B transmits all data contained in itf/irf at that time point, using a cycle start shortly after the issuing of itgo. in isochronous transmission, when packets have been trans- mitted, packet data are flushed from the itf/irf. unlike the previous modes, buffer control for reception is not reciprocally performed and one-directional fifo control is effected. for reception, a maximum of 4 different channels can be received, set by the isochronous configuration register. the MD8412B automatically flushes the packet under the conditions that there is no empty area in the buffer for the received quantity of packet data, there is a crc error in the packet header and pay-load area, and there is no coincidence between the header length value and the quantity of data in actual pay-load area. 5-3-4-2-2 auto-mode in auto-mode, one sub-buffer is assigned to one channel. accordingly, the total number of channels applicable to trans- mission/reception is limited to 2. the combination is dependent on the isomode register. in the reception mode of two channels for isomode="011" buffering is effected through routing to the two sub-buffers, according to the respective reception channels set by each isochronous configuration register. unlike the other modes, buffer control is not recipro- cally performed and one-directional fifo control is effected. during transmission, the MD8412B reads out data from the buffer for the amount of preset transmission data length value, and packet transmission is effected in synchronization with cycle start. if the quantity of data in the buffer is not enough to attain the preset length value at that time, packet transmi s- sion in that cycle is not effected, but a condition is waited until the specified amount of data has been written by the host. in this way, the host is not conscious of buffer writing in packet unit and data streams are written so that the transmission buffer itf/irf is not full. even in reception, one-directional fifo control takes place, but the unit of announcement to the host is that of individual packet reception. under the same condition as for the isochronous normal reception mode, the objective packets are auto- matically flushed.
MD8412B ver 1.10 fujifuilm microdevices co., ltd. 77 5-4 isochronous transfer control (auto-mode) isochronous data transfer is conducted either in normal mode or in auto-mode. in the normal mode, the host uses a packet and its header for buffer writing in the MD8412B during transmission in the same manner as for asynchronous data transfer. at that time, itgo is issued for a different channel in the unit of packet group, in order to send a transmission request to th e MD8412B. during reception also, reading is started in the unit of packet group inclusive of the header when the MD8412B has received the packet. in the auto-mode, on the other hand, insertion of the isochronous packet header is conducted by the MD8412B during trans- mission, and separation of this header is conducted during reception. in this fashion, the host can gain access to the MD8412B in the unit of data stream to be transferred, not in the concept of packets. for transmission in the auto-mode, the number of channels is limited to one. for reception, the number of channels is limited to two at the maximum. for data transfer with more channels, it is always carried out in the normal mode. for transmission, the host makes necessary information setting in advance in the header part of the isochronous packet in the isochronous configuration register. the MD8412B generates a header based on the contents of this register. 5-4-1 length control the data in the itf are converted into a packet in the unit of length set in the isochronous packet length register, and this packet is transmitted with the timing of each cycle start. the value of this register is used as the datalength field in the is o- chronous packet header. if the data in the itf are not enough for the value of length set at the timing of a certain cycle start, the MD8412B does not perform transmission at that timing, but waits for the next transmission until the data amounting to the required length are accumulated in the buffer. in this case, this condition is announced to the host with the itnotx bit in the interrupt reg- ister. the isochronous packet length register is set in the unit of bytes. however, if setting is made in the isochronous packet length register not in the unit of quadlet but in the unit of effective bits for the lower two bits, the MD8412B rounds up this value to the quadlet value required for transmission. as described above, if each packet makes data setting in the isochro- nous packet length register not in the quadlet unit, it is then necessary for the host side to write the data in the itf, for which padding treatment has been finished so that the quadlet unit becomes available. 5-4-2 transmission start / stop control the itstart terminal and the itstart bit in the tgo register are used during transmission in the auto-mode, so that information about the start of packet transmission can be sent to the MD8412B. when the itstart terminal and the itstart bit are asserted, the MD8412B begins to perform transmission for the packet length that is preset in the isochronous packet length register, starting with the start packet that has been placed shortly after the above-mentioned assertion. when the itstart terminal and the itstart bit are negated, the MD8412B then performs transmission of one packet shortly after the placement of the start packet and stops further transmission. the relationship between the itstart terminal and the itstart bit is expressed by a logical sum (or). therefore, oper- ation can be issued from the system to either hardware set or software set. at the itstart terminal, transmission is started with a transition from the "0" to "1" level, and stopped with another transition from the "1" to "0" level. similarly a s for the itstart bit, transmission is started with the writing of "1" and stopped with another writing of "0". 5-4-3 sync control during transmission, the MD8412B can insert three types of codes in the synchronization code field of the isochronous header. during reception, it can perform reception control based on the contents of the synchronization code field. when the syncen bit is "0" in the isochronous configuration register, contents of the setting value of the sync register in that register are entered in the synchronization code field in the packet header at any time.
MD8412B 78 fujifuilm microdevices co., ltd. ver 1.10 when syncen = "1" during transmission, the value preset in the startsync register is entered in the synchronization code field of the first packet that is transmitted with itstart. the values of the sync register are then entered in the packets tha t are sent secondly and thereafter. when transmission stop is effected with itstop, the value of the stopsync register is entered in the last packet that is transmitted shortly thereafter. in this manner, the respective values can automatically be entered in the synchronization code field of the packet that is sent at first, the packet that is sent last, or the packet that is sent in succession. during reception, based on the value in the synchronization code field of the received isochronous packet, reception is started with that packet when the contents coincide with those of the startsync register. if the contents coincide with those of the stopsync register, that packet is received first, then operation for packet reception can be stopped. 5-5 cycle master to maintain isochronous operation, a cycle master is always required on the bus. to obtain this cycle master, it is neces- sary to generate a cycle start event to be triggered by a cycle_time register that is synchronized with the 8khz clock. this function is incorporated in the MD8412B which, therefore, has a capability of being a cycle master. to become a cycle master, the cyclemaster bit is set at "1" this is, however, possible only if there is an announcement that the own node is a route. being a cycle master, a cycle start packet is generated, synchronized with the cycle start event. it i s controlled by the cycletimeren bit. the 8khz frequency, being a clock for the cycle start event generated in the cycle master, is obtained through internal fre- quency division from 49.152mhz of the master clock supplied from the phy-chip, or by feeding an external 8khz to the cyclein terminal. therefore, selection is needed. this setting is controlled by the cyclesource bit. 5-6 32-bit crc the packet data transmitted from the MD8412B are attached with a 32-bit crc at the header block and the data block, as defined in the p1394 draft. during reception, crc is computed from data at the header block and the data block, in order to make comparison with the crc data attached in the received packet. if there is no coincidence as a result of comparison, an announcement is given to the hdrerr bit located in the interrupt register or the ackstatus bit of the diagnostic status registe r. the following expression is used as the crc polynomial: x32 + x30 + x26 + x25 + x24 + x18 + x15 + x14 + x12 + x11 + x10 + x9 + x6 + x5 + x4 + x3 + x + 1 5-7 control flow when the power supply is turned on, the MD8412B is set in the following procedures: 1) reset# is asserted to reset the device. 2) even after the reset operation has been completed, the MD8412B can perform setting in conjunction with the host. it is, however, impossible to perform communication or communication with the phy. first of all, the initial values of the MD8412B (buffer capacity setting) must be set up. 3) upon completion of initial setting, connections are made toward the phy in order to perform communication. this can be realized by setting up the linkon bit (control register). 4) when linkon is set at "1", ommunication becomes possible with the phy, and further setting becomes possible for, such as, the acquisition of nodeid, communication with the transceiver, receiver, etc., and so on. at the above-mentioned stage, initial setting can be finished at the time of power on. the subsequent steps for data transfer are possible according to the communication flow specified below.
MD8412B ver 1.10 fujifuilm microdevices co., ltd. 79 5-7-1 asynchronous transmission figure 5-7-1 atf transmission flow -1 size buffer(atf) host i/f phy i/f empty full arbitration won ack_complete ack transmit arbitration won transmit transmit ack_busy ack ack arbitration won ack_complete retry phase arbitration won ack_complete transmit ack atf register write (packet1) ago int#(atxend) atf register write (packet2) ago atf register write (packet3) ago int#(atxend) int#(atxend) (2) (3) (1)
MD8412B 80 fujifuilm microdevices co., ltd. ver 1.10 figure 5-7-2 atf transmission flow -2 size buffer(atf) host i/f phy i/f empty full arbitration won ack_complete ack transmit transmit ack arbitration won ack_complete atf register write (packet1) ago atf register write (packet2) int#(atxend) atf register write (packet2 continue) ago int#(atxend) (2) atffull (1)
MD8412B ver 1.10 fujifuilm microdevices co., ltd. 81 5-7-2 asynchronous reception figure 5-7-3 arf reception flow -1 size buffer(arf) host i/f phy i/f empty full ack_complete ack receive receive receive ack_complete ack ack ack_busy arf register read (packet1) int#(arxend) arf register read (packet2) arfflush int#(arxend) (2) (3) (1) int#(arxend) arstatus arempty arempty
MD8412B 82 fujifuilm microdevices co., ltd. ver 1.10 figure 5-7-4 arf reception flow -2 size buffer(arf) host i/f phy i/f empty full ack_complete ack receive receive ack ack_complete arf register read (packet1) int#(arxend) arf register read (packet2) int#(arxend) (3) (1) int#(arxend) receive ack_complete ack arf register read (packet3) arempty (2)
MD8412B ver 1.10 fujifuilm microdevices co., ltd. 83 the table below shows how information is distributed in regard to the status and interruption that indicate the state of reception performed according to the flow shown above. status when normal reception is impossible as a result that fifo becomes full in the middle of reception. when normal reception has been accomplished. when the capacity of arf vacancy is 4quadlet or less at the start of reception. when the capacity of arf vacancy is 5quadlet or less at the start of reception. arxend interrupt 0 0 1 sentrej interrupt 1 1 0 arfflush interrupt 1 1 0 arf state the same condition as that before reception. nothing is written. the same condition as that before reception. nothing is written. everything stored. table 5-7-1 status of interrupt and fifo during arf reception
MD8412B 84 fujifuilm microdevices co., ltd. ver 1.10 5-7-3 isochronous transmission figure 5-7-5 itf transmission flow size buffer(itf) host i/f phy i/f empty full arbitration won transmit itf register write (packets1) igo itf register write (packets2) igo int#(cyclestart) itffull (1) igo write(packets3) int#(cyclestart) won int#(cyclestart) arbitration won transmit arbitration transmit (2) (3) 125s cyclestart 125s cyclestart cyclestart
MD8412B ver 1.10 fujifuilm microdevices co., ltd. 85 5-7-4 isochronous reception figure 5-7-6 irf reception flow size buffer(irf) host i/f phy i/f empty full receive itf register read (packet1) int#(irxend) itf register read (packet2) int#(irfflush) (2) (1) int#(irxend) int#(cyclestart) int#(cyclestart) int#(cyclestart) receive receive (3) 125s cyclestart cyclestart 125s cyclestart 125s
MD8412B 86 fujifuilm microdevices co., ltd. ver 1.10 5-7-5 isochronous transmission (auto-mode) figure 5-7-7 itf transmission flow (auto-mode & syncen="1") size buffer(itf) host i/f phy i/f empty full no transmit itf register write itstart assert "h" int#(cyclestart) itstart negate "l" cyclestart cyclestart transmit with "startsync" cyclestart transmit with "sync" cyclestart transmit with "sync" cyclestart no transmit (fifo empty) cyclestart transmit with "stopsync" itf register write no transmit cyclestart (full)
MD8412B ver 1.10 fujifuilm microdevices co., ltd. 87 5-7-6 isochronous reception (auto-mode) figure 5-7-8 irf reception flow (auto-mode & syncen="1") size buffer(irf) host i/f phy i/f empty full itf register read int#(irxend) cyclestart cyclestart cyclestart receive(3) cyclestart receive(5) with "stopsync" full a iso packet with no "startsync" (don?t accept) receive(1) with "startsync" receive(2) cyclestart receive(4) cyclestart a iso packet with no "startsync" (don?t accept) int#(irfflush) itf register read (auto flush) cyclestart
MD8412B 88 fujifuilm microdevices co., ltd. ver 1.10 the table below shows how information is distributed in regard to the status and interruption that indicate the state of reception performed according to the flow shown above. status when normal reception is impossible as a result that fifo becomes full in the middle of reception. when normal reception has been accomplished. when the capacity of irf, itf/irf vacancy is 4quadlet or less at the start of reception. when the capacity of irf, itf/irf vacancy is 5quadlet or less at the start of reception. irxend itr/irfrxend interrupt 001 sentrej interrupt 110 irfflush itf/irfflush bit 110 status of irf itf/irf nothing is written. nothing is written. everything stored. table 5-7-2 status of interrupt and fifo during irf, tf/irf reception
MD8412B ver 1.10 fujifuilm microdevices co., ltd. 89 5-8 asynchronous stream transfer flow the MD8412B is provided with the various functions by which the asynchronous stream can be transferred. during trans- mission or reception, the following controls are carried out. 5-8-1 asynchronous stream transmission during transmission, the asynchronous stream packet is sent to the atf buffer as shown in the table below. at that time, 1quadlet of the identification data, which is the asynchronous stream packet, is inserted before the isochronous packet for- mat and atgo is then issued. in this manner, the following packet is transmitted as an asynchronous stream packet. in this case, however, the relationship of tcode=0xa is required to hold. the data being transmitted actually are those of 2quadlet and thereafter. for the asynchronous stream packet transmission, arbitration is carried out in the same manner as for ordi- nary asynchronous performance, and data are transmitted to a party other than the isochronouscycle. the header crc and the payload crc are automatically generated inside the MD8412B and both are added before trans- mission. 5-8-2 asynchronous stream reception when a packet, which coincides with the channel of the asynchronous stream, is detected during reception, the MD8412B stores it in the arf buffer. the data format is as specified below. at that time, the relationship of tcode=0xa holds. the last acksent indicates the status of reception at the MD8412B. the same value as that for the asynchronous reception is stored. if the arf buffer is full in this case, the arfflush interrupt occurs and no data are stored in the arf buffer. (this is not an interrupt of the isochronous system.) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 spd tcode reserved datalength tag channel sy asynchronous stream data padding (if necessary) table 5-8-1 asynchronous stream transmit format 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 datalength tag channel tcode sy asynchronous stream data spd errcode table 5-8-2 asynchronous stream receive format
MD8412B 90 fujifuilm microdevices co., ltd. ver 1.10 5-9 command-reset packet processing when a command-reset packet (a packet addressed to the reset area in the csr space) is received, the md8412a may per- form such a processing that the cmdreset bit is set at "1" in the interrupt register without storing it in the buffer. in the c ase of the MD8412B, however, the command-reset packet is received and stored in the arf buffer, and the cmdreset bit is set at "1" in the interrupt register. however, if there is no vacancy in the arf buffer, only processing is carried out for the cmdreset interrupt. 5-10 bus number for asynchronous packet transmission for packet transmission, the MD8412B is provided with the various functions by which the bus number of the own node defined in the ieee1212 space is incorporated in the source area and the header area of the ieee1394 packet format. the incorporated value is either the value set with the busnumber bit in the MD8412B register or "3ffh" according to the result of selection at that time. in order to make the set value be valid in the MD8412B register, it is necessary to set up the busid bit of the first quadlet a t "0b" in the asynchronous quadlet/block transmit format. to make the bus number be a fixed value of "3ffh", it is necessary for the busid bit to be set at "1b". if the busid bit is set at "1b", the set value of the MD8412B register becomes invalid.
MD8412B ver 1.10 fujifuilm microdevices co., ltd. 91 6 electrical characteristics (preliminary) 6-1 absolute rating 6-2 recommended operating condition ( v ss = 0v) symbol parameter rating units vdd supply voltage -0.3 ~ 4.6 v vi1 *1 input voltage -0.3 ~ 6.5 v vi2 -0.3 ~ vdd+0.5 v vout output voltage -0.3 ~ vdd+0.5 v tstg storage temp. -40 ~ +125 c *i/o terminal except d(7:0), ctl(1:0), sclk, lreq, lps and output terminal. (v ss = 0v) symbol parameter rating units vdd power voltage 3.0 ~ 3.6 v vi1 *1 input voltage 0 ~ 5.5 v vi2 0 ~ vdd v tstg storage temp. 0 ~ 70 c *i/o terminal except d(7:0), ctl(1:0), sclk, lreq, lps and output terminal.
MD8412B 92 fujifuilm microdevices co., ltd. ver 1.10 6-3 dc characteristics electrical characteristics under the recommended operating conditions (unless otherwise specified) ( v ss=0v) symbol item pin test condition min typ max unit vih high level input voltage sclk, ctl, d vref = vdd/2 0.1% vref+0.3 vref+0.9 v else vdd = max 2.0 vil low level input voltage sclk, ctl, d vref = vdd/2 0.1% vref-0.9 vref-0.3 v else vdd = min 0.8 voh high level output voltage lps, lreq, ctl, d ioh = -12ma vdd-0.4 v else ioh = -6ma vol low level output voltage lps, lreq, ctl, d ioh = 12ma 0.4 v else ioh = 6ma idd dynamic current (5v) vdd vdd = 3.3v - 60 191 ma
MD8412B ver 1.10 fujifuilm microdevices co., ltd. 93 6-4 ac characteristics symbol item min typ max unit t css cs#, dack# setup time 5 ns t cswh cs#, dack# holdtime (write) 0 ns t csrh cs#, dack# hold time (read) 0 ns t ads ha, uwe#, ube# setup time 30 ns t adh ha, uwe#, ube# hold time 5 ns t rw read write pulse width 30 ns t rwc1 read/write cycle time 1 90 ns t rwc2 read/write cycle time 2 40 ns t dtd read data output delay time 15 ns *1 t dth read data output hold time 1 30 ns *1 t wrds write data setup time 10 ns t wrdh write data hold time 2 ns t rsw reset pulse width 160 ns t cycd cycleout output delay 4 17 ns *1 *1: load capacitor 50pf *1: load capacitor 20pf table 6-4-1 host interface ac characteristics
MD8412B 94 fujifuilm microdevices co., ltd. ver 1.10 figure 6-4-1 host interface ac characteristics (read/write) t dth t dtd t csrh t rwc2 t rw t css t rwc1 t wrds t wrdh t cswh t rwc2 t rw t rwc1 t css t ads t adh ube# cs# wr# hd(31:0) write rd# hd(31:0) read uwe# ha(6:0) t ads t adh
MD8412B ver 1.10 fujifuilm microdevices co., ltd. 95 figure 6-4-2 host interface ac characteristics (reset) figure 6-4-3 interface ac characteristics (dma) figure 6-4-4 host interface ac characteristics (cyclein/out) t rsw reset# t rwc2 t rw t css t wrds t wrdh t cswh t rwc2 t rw dack# wr# hd(31:0) write t dth t dtd t csrh rd# hd(31:0) read t css t rwc1 t rwc1 t cycd sclk cycleout
MD8412B 96 fujifuilm microdevices co., ltd. ver 1.10 figure 6-4-5 phy ac characteristics (sclk) symbol item min typ max unit t ctd control output delay 1 10 ns t pdd phy data output delay 1 10 ns t cts control setup 6 ns t cth control hold 0 ns t pds phy data setup 6 ns t pdh phy data hold 0 ns t lrd lreq data output delay 1 10 ns t sckc sclk cycle time 20 ns t sckh sclk high level time 8 12 ns t sckl sclk low level time 8 12 ns t lpsc lps cycle time 360 570 ns t lpsh lps high level time 175 290 ns t lpsl lps low level time 175 290 ns (condition: load capacitor 50pf) table 6-4-2 phy ac characteristics t sckh sclk t sckl t sckc
MD8412B ver 1.10 fujifuilm microdevices co., ltd. 97 figure 6-4-6 phy ac characteristics (ctl, d) figure 6-4-7 phy ac characteristics (lreq) figure 6-4-8 phy ac characteristics (lps) t ctd t cts sclk ctl(1:0) d(7:0) d(7:0) t pdd transmit ctl(1:0) receive t ctd t pdd t cth t pds t pdh sclk lreq t lrd t lpsh lps t lpsl t lpsc
MD8412B 98 fujifuilm microdevices co., ltd. ver 1.10 7 pin assignment and package outline 7-1 pin assignment hd30 hd31 vss hd29 hd28 hd27 vdd hd26 hd25 hd24 vss hd23 hd22 hd21 vss hd20 hd19 hd18 vdd hd17 hd16 hd15 vss hd14 hd13 lreq lps vss sclk vss ctl0 crl1 vdd d0 d1 vss d2 d3 vdd d4 d5 vss d6 d7 vdd direct test0 test1 inp2 inp0 vss hd12 hd11 hd10 hd9 vdd hd8 hd7 hd6 vss hd5 hd4 hd3 vdd hd2 hd1 hd0 vss itstart inp1 testen tlink vss tlinksep trful ha1 ha0 vss ha2 ha3 ha4 vdd ha5 ha6 cs# vss wr# rd# uwe# vdd ube# dack# dreq vss int# reset# vdd cycleout cyclein vss 100 50 40 30 1 10 20 60 70 80 90
MD8412B ver 1.10 fujifuilm microdevices co., ltd. 99 7-2 package outline 0.5 16.00.4 14.00.1 51 75 25 1 50 26 76 100 16.00.4 14.00.1 min 0.13 nom 0.18 max 0.28 12 12 0.1 1.40.1 1.70max m i n 0 . 1 n o m 0 . 1 2 5 m a x 0 . 1 7 5 0 ~ 10 0.5 0.50.2 1.0 0.28
MD8412B 100 fujifuilm microdevices co., ltd. ver 1.10 appendix 1 i/o status pin i/o poweron reset# low normal sclk i hi-z lreq o ctl(1:0) i/o d(7:0) i/o ha(6:0) i hi-z hd(31:0) i/o when rd# is "h" hi-z wr# i hi-z rd# i hi-z cs# i hi-z uwe# i hi-z ube# i hi-z dreq o n/a low low/high dack# i hi-z int# o n/a high low/high reset# i hi-z cyclein i hi-z cycleout o itstart i hi-z
MD8412B ver 1.10 fujifuilm microdevices co., ltd. 101 appendix 2 example circuit for ac connection 1) lreq, ctl(0:1), d(0:7) 2) sclk 3) lps MD8412B md8404 vdd(8412b) vdd(8404) vss(8412b) vss(8404) 5.1k 1% 5.1k 1% 5.1k 1% 5.1k 1% 300 1% 0.001 50v 0.001 50v MD8412B md8404 vdd(8412b) vdd(8404) vss(8412b) vss(8404) 5.1k 1% 5.1k 1% 5.1k 1% 5.1k 1% 0.001 50v sclk sclk 100 1% MD8412B md8404 vdd(8404) vss(8404) 6.8k 5% 2.7k 5% 33n 50v lps lps 510 5%
MD8412B 102 fujifuilm microdevices co., ltd. ver 1.10 notes - contents of this manual may be modified without notice. - partial or overall reproduction and reprinting of this manual shall be prohibited without permission of the company. - owing this manual shall not fall out permission for the use of industrial and copy rights reserved by the company and fuji photo film co., ltd. the company shall not be responsible for industrial and copy rights of the third party. - the company shall not be responsible for any damage caused from this manual and from this chip. - prior to use, exchange of invoice specifications is required. - information available from: - head office 1-6, matsusakadaira, taiwa-cho kurokawa-gun, miyagi, 981-34 japan tel: 81-22-347-1128 fax: 81-22-347-1136 - tokyo office fukumasu bldg. 6f 1-20, ageba-cho, shinjuku-ku tokyo, 162 japan tel: 81-3-3269-2141 fax: 81-3-5229-7381

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